diff options
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/acpi.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 11 | ||||
| -rw-r--r-- | src/soc/intel/skylake/cpu.c | 7 | ||||
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage.c | 3 |
4 files changed, 5 insertions, 18 deletions
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 2af5a53149..332f797dbb 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -205,7 +205,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; - if (config->sgx_enable) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) sgx_fill_gnvs(gnvs); } diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 944315b47e..636266632e 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -510,14 +510,6 @@ struct soc_intel_skylake_config { */ u8 SendVrMbxCmd; - /* - * PRMRR size setting with three options - * 0x02000000 - 32MiB - * 0x04000000 - 64MiB - * 0x08000000 - 128MiB - */ - u32 PrmrrSize; - /* Enable/Disable host reads to PMC XRAM registers */ u8 PchPmPmcReadDisable; @@ -576,9 +568,6 @@ struct soc_intel_skylake_config { u8 SlowSlewRateForGt; u8 SlowSlewRateForSa; - /* Enable SGX feature */ - u8 sgx_enable; - /* Enable/Disable EIST * 1b - Enabled * 0b - Disabled diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index bfed528a06..080dba0b13 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -442,8 +442,6 @@ static void cpu_lock_aesni(void) /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { - config_t *conf = config_of_soc(); - /* Clear out pending MCEs */ /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears @@ -479,7 +477,7 @@ void soc_core_init(struct device *cpu) enable_turbo(); /* Configure Core PRMRR for SGX. */ - if (conf->sgx_enable) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) prmrr_core_configure(); } @@ -502,7 +500,6 @@ static void fc_lock_configure(void *unused) static void post_mp_init(void) { int ret = 0; - config_t *conf = config_of_soc(); /* Set Max Ratio */ cpu_set_max_ratio(); @@ -519,7 +516,7 @@ static void post_mp_init(void) ret |= mp_run_on_all_cpus(vmx_configure, NULL); - if (conf->sgx_enable) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) ret |= mp_run_on_all_cpus(sgx_configure, NULL); ret |= mp_run_on_all_cpus(fc_lock_configure, NULL); diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index af89441194..a72b261a56 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <device/pci_def.h> #include <fsp/util.h> +#include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <memory_info.h> #include <smbios.h> @@ -237,7 +238,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->CmdTriStateDis = config->CmdTriStateDis; m_cfg->DdrFreqLimit = config->DdrFreqLimit; m_cfg->VmxEnable = CONFIG(ENABLE_VMX); - m_cfg->PrmrrSize = config->PrmrrSize; + m_cfg->PrmrrSize = get_prmrr_size(); for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) mask |= (1<<i); |