4 files changed, 10 insertions, 11 deletions

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 4c055ea1df..b86d002bc2 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -53,12 +53,12 @@ config CPU_SPECIFIC_OPTIONS
 
 config CHROMEOS
 	select CHROMEOS_RAMOOPS_DYNAMIC
-	select CHROMEOS_VBNV_CMOS
-	select CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH
 	select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC
 	select VBOOT_EC_SLOW_UPDATE
 	select VBOOT_OPROM_MATTERS
 	select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
+	select VBOOT_VBNV_CMOS
+	select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
 	select VIRTUAL_DEV_SWITCH
 
 config BOOTBLOCK_CPU_INIT
diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c
index 4bb597c64c..209d22c8cf 100644
--- a/src/soc/intel/skylake/igd.c
+++ b/src/soc/intel/skylake/igd.c
@@ -16,6 +16,7 @@
 
 #include <arch/acpi.h>
 #include <arch/io.h>
+#include <bootmode.h>
 #include <chip.h>
 #include <console/console.h>
 #include <delay.h>
@@ -31,7 +32,7 @@
 #include <soc/systemagent.h>
 #include <stdlib.h>
 #include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
+#include <vboot/vbnv.h>
 
 u32 map_oprom_vendev(u32 vendev)
 {
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index 6b7a17b6a9..a8ec7b6a8e 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -35,10 +35,8 @@
 #include <cpu/x86/smm.h>
 #include <soc/pcr.h>
 #include <soc/ramstage.h>
-#if IS_ENABLED(CONFIG_CHROMEOS)
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <vendorcode/google/chromeos/vbnv_layout.h>
-#endif
+#include <vboot/vbnv.h>
+#include <vboot/vbnv_layout.h>
 
 static const struct reg_script pch_pmc_misc_init_script[] = {
 	/* SLP_S4=4s, SLP_S3=50ms, disable SLP_X stretching after SUS loss. */
@@ -108,14 +106,14 @@ static void pch_set_acpi_mode(void)
 	}
 }
 
-#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)
+#if IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS)
 /*
  * Preserve Vboot NV data when clearing CMOS as it will
  * have been re-initialized already by Vboot firmware init.
  */
 static void pch_cmos_init_preserve(int reset)
 {
-	uint8_t vbnv[VBNV_BLOCK_SIZE];
+	uint8_t vbnv[VBOOT_VBNV_BLOCK_SIZE];
 	if (reset)
 		read_vbnv(vbnv);
 
@@ -143,7 +141,7 @@ static void pch_rtc_init(void)
 	/* Ensure the date is set including century byte. */
 	cmos_check_update_date();
 
-#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS)
+#if IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS)
 	pch_cmos_init_preserve(rtc_failed);
 #else
 	cmos_init(rtc_failed);
diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c
index 209beebe0f..cf75ccb750 100644
--- a/src/soc/intel/skylake/romstage/power_state.c
+++ b/src/soc/intel/skylake/romstage/power_state.c
@@ -30,7 +30,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/romstage.h>
-#include <vendorcode/google/chromeos/vboot_common.h>
+#include <vboot/vboot_common.h>
 
 static struct chipset_power_state power_state CAR_GLOBAL;