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-rw-r--r--src/soc/intel/skylake/chip.c3
-rw-r--r--src/soc/intel/skylake/chip.h8
2 files changed, 0 insertions, 11 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 5b05dd20b2..88f432de01 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -256,9 +256,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
dev = pcidev_path_on_root(PCH_DEVFN_CSE_3);
params->Heci3Enabled = dev && dev->enabled;
- params->LogoPtr = config->LogoPtr;
- params->LogoSize = config->LogoSize;
-
params->CpuConfig.Bits.VmxEnable = CONFIG(ENABLE_VMX);
params->PchPmWoWlanEnable = config->PchPmWoWlanEnable;
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index e5592b4358..bef0f122c9 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -288,14 +288,6 @@ struct soc_intel_skylake_config {
u8 SkipExtGfxScan;
u8 ScanExtGfxForLegacyOpRom;
- /*
- * The following fields come from fsp_vpd.h
- * These are configuration values that are passed to FSP during
- * SiliconInit.
- */
- u32 LogoPtr;
- u32 LogoSize;
-
/* GPIO IRQ Route The valid values is 14 or 15*/
u8 GpioIrqSelect;
/* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23*/