diff options
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/Makefile.inc | 5 | ||||
| -rw-r--r-- | src/soc/intel/skylake/bootblock/pch.c | 7 | ||||
| -rw-r--r-- | src/soc/intel/skylake/bootblock/smbus.c | 46 | ||||
| -rw-r--r-- | src/soc/intel/skylake/early_smbus.c | 30 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/bootblock.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pm.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/smbus.h | 24 | ||||
| -rw-r--r-- | src/soc/intel/skylake/smbus.c | 110 | ||||
| -rw-r--r-- | src/soc/intel/skylake/smbus_common.c | 151 |
10 files changed, 8 insertions, 369 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index fba6f7f0b9..475c88311c 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -58,6 +58,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_LPSS_I2C diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 1d8fe168fb..d25332c93a 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -14,7 +14,6 @@ bootblock-y += bootblock/cpu.c bootblock-y += bootblock/i2c.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c -bootblock-y += bootblock/smbus.c bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c bootblock-y += gpio.c @@ -44,8 +43,6 @@ romstage-y += pch.c romstage-y += pei_data.c romstage-y += pmutil.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c -romstage-y += smbus_common.c -romstage-y += early_smbus.c romstage-y += spi.c romstage-y += tsc_freq.c romstage-$(CONFIG_UART_DEBUG) += uart_debug.c @@ -77,8 +74,6 @@ ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-y += sata.c ramstage-y += sd.c ramstage-y += sgx.c -ramstage-y += smbus.c -ramstage-y += smbus_common.c ramstage-y += smi.c ramstage-y += smmrelocate.c ramstage-y += spi.c diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index a92e4cffba..780c4aa235 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -22,6 +22,7 @@ #include <intelblocks/itss.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> +#include <intelblocks/smbus.h> #include <soc/bootblock.h> #include <soc/iomap.h> #include <soc/lpc.h> @@ -182,14 +183,14 @@ static void soc_config_tco(void) /* Disable TCO in SMBUS Device first before changing Base Address */ reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL); - reg32 &= ~SMBUS_TCO_EN; + reg32 &= ~TCO_EN; pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32); /* Program TCO Base */ pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDDRESS); /* Enable TCO in SMBUS */ - pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | SMBUS_TCO_EN); + pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_EN); /* * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] @@ -269,7 +270,7 @@ void pch_early_init(void) pch_enable_lpc(); /* Program SMBUS_BASE_ADDRESS and Enable it */ - enable_smbus(); + smbus_common_init(); /* Set up GPE configuration */ pmc_gpe_init(); diff --git a/src/soc/intel/skylake/bootblock/smbus.c b/src/soc/intel/skylake/bootblock/smbus.c deleted file mode 100644 index 14a9666176..0000000000 --- a/src/soc/intel/skylake/bootblock/smbus.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/pci_ids.h> -#include <device/pci_def.h> -#include <reg_script.h> -#include <soc/bootblock.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/smbus.h> - -static const struct reg_script smbus_init_script[] = { - /* Set SMBUS I/O base address */ - REG_PCI_WRITE32(SMB_BASE, SMBUS_BASE_ADDRESS | 1), - /* Set SMBUS enable */ - REG_PCI_WRITE8(HOSTC, HST_EN), - /* Enable I/O access */ - REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO), - /* Disable interrupts */ - REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0), - /* Clear errors */ - REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff), - /* Indicate the end of this array by REG_SCRIPT_END */ - REG_SCRIPT_END, -}; - -void enable_smbus(void) -{ - reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script); -} diff --git a/src/soc/intel/skylake/early_smbus.c b/src/soc/intel/skylake/early_smbus.c deleted file mode 100644 index 6df971a35b..0000000000 --- a/src/soc/intel/skylake/early_smbus.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/smbus_def.h> -#include <device/early_smbus.h> -#include <soc/smbus.h> -#include <soc/iomap.h> - -u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset) -{ - return do_smbus_read_byte(SMBUS_BASE_ADDRESS, addr, offset); -} - -u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value) -{ - return do_smbus_write_byte(SMBUS_BASE_ADDRESS, addr, offset, value); -} diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index f290d0f668..10c8de1241 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -30,7 +30,6 @@ void bootblock_pch_early_init(void); void pch_uart_init(void); /* Bootblock post console init programing */ -void enable_smbus(void); void i2c_early_init(void); void pch_early_init(void); void pch_early_iorange_init(void); diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 7112c77a24..15c291cc96 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -51,7 +51,7 @@ #define INTEL_USB2_EN (1 << 18) #define LEGACY_USB2_EN (1 << 17) #define PERIODIC_EN (1 << 14) -#define TCO_EN (1 << 13) +#define TCO_SMI_EN (1 << 13) #define MCSMI_EN (1 << 11) #define BIOS_RLS (1 << 7) #define SWSMI_TMR_EN (1 << 6) diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h index 1e4d59bc24..ad5ae2611c 100644 --- a/src/soc/intel/skylake/include/soc/smbus.h +++ b/src/soc/intel/skylake/include/soc/smbus.h @@ -20,14 +20,12 @@ #define _SOC_SMBUS_H_ /* PCI Configuration Space (D31:F3): SMBus */ -#define SMB_BASE 0x20 -#define HOSTC 0x40 -#define HST_EN (1 << 0) #define SMB_RCV_SLVA 0x09 + /* SMBUS TCO base address. */ #define TCOBASE 0x50 #define TCOCTL 0x54 -#define SMBUS_TCO_EN (1 << 8) +#define TCO_EN (1 << 8) /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ #define TCO1_STS 0x04 @@ -39,24 +37,6 @@ #define TCO_TMR_HLT (1 << 11) /* SMBus I/O bits. */ -#define SMBHSTSTAT 0x0 -#define SMBHSTCTL 0x2 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBBLKDAT 0x7 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf - -#define SMBUS_TIMEOUT (10 * 1000 * 100) #define SMBUS_SLAVE_ADDR 0x24 -int do_smbus_read_byte(unsigned int smbus_base, unsigned int device, - unsigned int address); -int do_smbus_write_byte(unsigned int smbus_base, unsigned int device, - unsigned int address, unsigned int data); - #endif diff --git a/src/soc/intel/skylake/smbus.c b/src/soc/intel/skylake/smbus.c deleted file mode 100644 index dc6c435324..0000000000 --- a/src/soc/intel/skylake/smbus.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/device.h> -#include <device/path.h> -#include <device/smbus.h> -#include <device/smbus_def.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <soc/iomap.h> -#include <soc/ramstage.h> -#include <soc/smbus.h> - -static void pch_smbus_init(device_t dev) -{ - struct resource *res; - u16 reg16; - - /* Enable clock gating */ - reg16 = pci_read_config32(dev, 0x80); - reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14)); - pci_write_config32(dev, 0x80, reg16); - - /* Set Receive Slave Address */ - res = find_resource(dev, PCI_BASE_ADDRESS_4); - if (res) - outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA); -} - -static int lsmbus_read_byte(device_t dev, u8 address) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - - return do_smbus_read_byte(res->base, device, address); -} - -static int lsmbus_write_byte(device_t dev, u8 address, u8 data) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return do_smbus_write_byte(res->base, device, address, data); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, -}; - -static void smbus_read_resources(device_t dev) -{ - struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = SMBUS_BASE_ADDRESS; - res->size = 32; - res->limit = res->base + res->size - 1; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Also add MMIO resource */ - res = pci_get_resource(dev, PCI_BASE_ADDRESS_0); -} - -static struct device_operations smbus_ops = { - .read_resources = &smbus_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .scan_bus = &scan_smbus, - .init = &pch_smbus_init, - .ops_smbus_bus = &lops_smbus_bus, - .ops_pci = &soc_pci_ops, -}; - -static const unsigned short pci_device_ids[] = { - 0x9d23, /* SunRisePoint LP */ - 0xa123, /* SunRisePoint H */ - 0 -}; - -static const struct pci_driver pch_smbus __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; diff --git a/src/soc/intel/skylake/smbus_common.c b/src/soc/intel/skylake/smbus_common.c deleted file mode 100644 index 63a4f8aad1..0000000000 --- a/src/soc/intel/skylake/smbus_common.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com> - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/device.h> -#include <device/path.h> -#include <device/smbus_def.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <soc/ramstage.h> -#include <soc/smbus.h> - -static void smbus_delay(void) -{ - inb(0x80); -} - -static int smbus_wait_until_ready(u16 smbus_base) -{ - unsigned int loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_base + SMBHSTSTAT); - } while (byte & 1); - return loops ? 0 : -1; -} - -static int smbus_wait_until_done(u16 smbus_base) -{ - unsigned int loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_base + SMBHSTSTAT); - } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0); - return loops ? 0 : -1; -} - -int do_smbus_read_byte(unsigned int smbus_base, unsigned int device, - unsigned int address) -{ - unsigned char global_status_register; - unsigned char byte; - - if (smbus_wait_until_ready(smbus_base) < 0) - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - - /* Setup transaction */ - /* Disable interrupts */ - outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); - /* Set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD); - /* Set the command/address... */ - outb(address & 0xff, smbus_base + SMBHSTCMD); - /* Set up for a byte data read */ - outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), - (smbus_base + SMBHSTCTL)); - /* Clear any lingering errors, so the transaction will run */ - outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); - - /* Clear the data byte... */ - outb(0, smbus_base + SMBHSTDAT0); - - /* Start the command */ - outb((inb(smbus_base + SMBHSTCTL) | 0x40), - smbus_base + SMBHSTCTL); - - /* Poll for transaction completion */ - if (smbus_wait_until_done(smbus_base) < 0) - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - - global_status_register = inb(smbus_base + SMBHSTSTAT); - - /* Ignore the "In Use" status... */ - global_status_register &= ~(3 << 5); - - /* Read results of transaction */ - byte = inb(smbus_base + SMBHSTDAT0); - if (global_status_register != (1 << 1)) - return SMBUS_ERROR; - return byte; -} - -int do_smbus_write_byte(unsigned int smbus_base, unsigned int device, - unsigned int address, unsigned int data) -{ - unsigned char global_status_register; - - if (smbus_wait_until_ready(smbus_base) < 0) - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - - /* Setup transaction */ - /* Disable interrupts */ - outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); - /* Set the device I'm talking too */ - outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD); - /* Set the command/address... */ - outb(address & 0xff, smbus_base + SMBHSTCMD); - /* Set up for a byte data read */ - outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), - (smbus_base + SMBHSTCTL)); - /* Clear any lingering errors, so the transaction will run */ - outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); - - /* Clear the data byte... */ - outb(data, smbus_base + SMBHSTDAT0); - - /* Start the command */ - outb((inb(smbus_base + SMBHSTCTL) | 0x40), - smbus_base + SMBHSTCTL); - - /* Poll for transaction completion */ - if (smbus_wait_until_done(smbus_base) < 0) { - printk(BIOS_ERR, "SMBUS transaction timeout\n"); - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - - global_status_register = inb(smbus_base + SMBHSTSTAT); - - /* Ignore the "In Use" status... */ - global_status_register &= ~(3 << 5); - - /* Read results of transaction */ - if (global_status_register != (1 << 1)) { - printk(BIOS_ERR, "SMBUS transaction error\n"); - return SMBUS_ERROR; - } - - return 0; -} |