diff options
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/acpi.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/bootblock/bootblock.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/bootblock.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/iomap.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/skylake/uart.c | 110 |
6 files changed, 46 insertions, 76 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 3e0158bbab..9412b03eb9 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -64,6 +64,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SGX select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_VMX select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_NHLT diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 5bed11878c..2c06b4bea1 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -648,7 +648,7 @@ unsigned long southbridge_write_acpi_tables(struct device *device, struct acpi_rsdp *rsdp) { current = acpi_write_dbg2_pci_uart(rsdp, current, - pch_uart_get_debug_controller(), + uart_get_device(), ACPI_ACCESS_SIZE_DWORD_ACCESS); current = acpi_write_hpet(device, current, rsdp); return acpi_align_current(current); diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index 1803694132..a2bcaaf9af 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -16,6 +16,7 @@ #include <bootblock_common.h> #include <drivers/i2c/designware/dw_i2c.h> #include <intelblocks/gspi.h> +#include <intelblocks/uart.h> #include <soc/bootblock.h> asmlinkage void bootblock_c_entry(uint64_t base_timestamp) @@ -32,7 +33,7 @@ void bootblock_soc_early_init(void) pch_early_iorange_init(); if (IS_ENABLED(CONFIG_UART_DEBUG)) - pch_uart_init(); + uart_bootblock_init(); } void bootblock_soc_init(void) diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index 59ce92a58d..f5065148d3 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -27,7 +27,6 @@ static inline void bootblock_fsp_temp_ram_init(void) {} /* Bootblock pre console init programming */ void bootblock_cpu_init(void); void bootblock_pch_early_init(void); -void pch_uart_init(void); /* Bootblock post console init programming */ void i2c_early_init(void); diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 475d79db71..628a272a54 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -25,11 +25,12 @@ #define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 #define PCH_PRESERVED_BASE_SIZE 0x02000000 -#define UART_DEBUG_BASE_0_SIZE 0x1000 +#define UART_BASE_SIZE 0x1000 #define UART_BASE_0_ADDRESS 0xfe030000 /* Both UART BAR 0 and 1 are 4KB in size */ #define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ - UART_DEBUG_BASE_0_SIZE * (x))) + UART_BASE_SIZE * (x))) +#define UART_BASE(x) UART_BASE_0_ADDR(x) #define EARLY_I2C_BASE_ADDRESS 0xfe040000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c index 1b4e96eb60..53d408aebc 100644 --- a/src/soc/intel/skylake/uart.c +++ b/src/soc/intel/skylake/uart.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation + * Copyright (C) 2015-2018 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,106 +14,74 @@ * GNU General Public License for more details. */ -#include <cbmem.h> -#include <console/uart.h> -#include <device/pci.h> +#include <console/console.h> #include <device/pci_def.h> #include <gpio.h> #include <intelblocks/lpss.h> #include <intelblocks/pcr.h> #include <intelblocks/uart.h> #include <soc/bootblock.h> -#include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> +#include <string.h> /* Serial IO UART controller legacy mode */ #define PCR_SERIAL_IO_GPPRVRW7 0x618 #define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx)) /* UART pad configuration. Support RXD and TXD for now. */ -static const struct pad_config uart_pads[][2] = { +const struct uart_gpio_pad_config uart_gpio_pads[] = { { - PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ - PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ + .console_index = 0, + .gpios = { + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */ + }, }, { - PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1_RXD */ - PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1_TXD */ + .console_index = 1, + .gpios = { + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */ + }, }, { - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */ - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */ + .console_index = 2, + .gpios = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ + }, } }; -#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM) -uintptr_t uart_platform_base(int idx) -{ - /* Same base address for all debug port usage. In reality UART2 - * is currently only supported. */ - return UART_BASE_0_ADDR(idx); -} -#endif +const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); -void pch_uart_init(void) +void soc_uart_set_legacy_mode(void) { - uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - - uart_common_init(pch_uart_get_debug_controller(), base); - - /* Put UART in byte access mode for 16550 compatibility */ - if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) { - pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, - PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE)); - - /* - * Dummy read after setting any of GPPRVRW7. - * Required for UART 16550 8-bit Legacy mode to become active - */ - lpss_clk_read(base); - } - - gpio_configure_pads(uart_pads[CONFIG_UART_FOR_CONSOLE], - ARRAY_SIZE(uart_pads[CONFIG_UART_FOR_CONSOLE])); -} - -#if !ENV_SMM -void pch_uart_read_resources(struct device *dev) -{ - pci_dev_read_resources(dev); - - /* Set the configured UART base address for the debug port */ - if (IS_ENABLED(CONFIG_UART_DEBUG) && uart_is_debug_controller(dev)) { - struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); - /* Need to set the base and size for the resource allocator. */ - res->base = UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE); - res->size = UART_DEBUG_BASE_0_SIZE; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | - IORESOURCE_FIXED; - } -} -#endif - -bool pch_uart_init_debug_controller_on_resume(void) -{ - global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - - if (gnvs) - return !!gnvs->uior; - - return false; + pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, + PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE)); + /* + * Dummy read after setting any of GPPRVRW7. + * Required for UART 16550 8-bit Legacy mode to become active + */ + lpss_clk_read(UART_BASE(CONFIG_UART_FOR_CONSOLE)); } -device_t pch_uart_get_debug_controller(void) +struct device *soc_uart_console_to_device(int uart_console) { - switch (CONFIG_UART_FOR_CONSOLE) { + /* + * if index is valid, this function will return corresponding structure + * for uart console else will return NULL. + */ + switch (uart_console) { case 0: - return PCH_DEV_UART0; + return (struct device *)PCH_DEV_UART0; case 1: - return PCH_DEV_UART1; + return (struct device *)PCH_DEV_UART1; case 2: + return (struct device *)PCH_DEV_UART2; default: - return PCH_DEV_UART2; + printk(BIOS_ERR, "Invalid UART console index\n"); + return NULL; } } |