diff options
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 5c5d8a94d9..0f0518aeaf 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -420,7 +420,7 @@ static void enable_pm_timer_emulation(void) /* Set PM1 timer IO port and enable*/ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TMR, msr); + wrmsr(MSR_EMULATE_PM_TIMER, msr); } /* All CPUs including BSP will run the following function. */ @@ -528,7 +528,7 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) * be reloaded after the core PRMRR MSRs are programmed. */ msr1 = rdmsr(MTRR_CAP_MSR); - msr2 = rdmsr(PRMRR_PHYS_BASE_MSR); + msr2 = rdmsr(MSR_PRMRR_PHYS_BASE); if (msr2.lo && (current_patch_id == new_patch_id - 1)) return 0; else |