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-rw-r--r--src/soc/intel/skylake/chip.c4
-rw-r--r--src/soc/intel/skylake/chip.h2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 4139570f64..549f403384 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -210,8 +210,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(params->PcieRpHotPlug));
for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];
- if (config->PcieRpAspm[i])
- params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1;
+ if (config->pcie_rp_aspm[i])
+ params->PcieRpAspm[i] = config->pcie_rp_aspm[i] - 1;
if (config->pcie_rp_l1substates[i])
params->PcieRpL1Substates[i] = config->pcie_rp_l1substates[i] - 1;
}
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 5befb01a91..2584d5d809 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -262,7 +262,7 @@ struct soc_intel_skylake_config {
AspmL1,
AspmL0sL1,
AspmAutoConfig,
- } PcieRpAspm[CONFIG_MAX_ROOT_PORTS];
+ } pcie_rp_aspm[CONFIG_MAX_ROOT_PORTS];
/* PCIe RP L1 substate */
enum {