1 files changed, 35 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/stage_cache.c b/src/soc/intel/skylake/stage_cache.c
new file mode 100644
index 0000000000..346e673cf5
--- /dev/null
+++ b/src/soc/intel/skylake/stage_cache.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <cbmem.h>
+#include <soc/smm.h>
+#include <stage_cache.h>
+#include <stdint.h>
+
+void stage_cache_external_region(void **base, size_t *size)
+{
+	/* The ramstage cache lives in the TSEG region.
+	 * The top of ram is defined to be the TSEG base address. */
+	u32 offset = smm_region_size();
+	offset -= CONFIG_IED_REGION_SIZE;
+	offset -= CONFIG_SMM_RESERVED_SIZE;
+
+	*base = (void *)(cbmem_top() + offset);
+	*size = CONFIG_SMM_RESERVED_SIZE;
+}