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path: root/src/soc/intel/skylake/romstage/romstage_fsp20.c
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Diffstat (limited to 'src/soc/intel/skylake/romstage/romstage_fsp20.c')
-rw-r--r--src/soc/intel/skylake/romstage/romstage_fsp20.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index b15fa89292..bb86c6300d 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -223,7 +223,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg,
* If PEG port is not defined in the device tree, it will be disabled
* in FSP
*/
- dev = SA_DEV_PEG0; /* PEG 0:1:0 */
+ dev = pcidev_on_root(SA_DEV_SLOT_PEG, 0); /* PEG 0:1:0 */
if (!dev || !dev->enabled)
m_cfg->Peg0Enable = 0;
else if (dev->enabled) {
@@ -238,7 +238,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg,
m_t_cfg->Peg0Gen3EqPh3Method = 0;
}
- dev = SA_DEV_PEG1; /* PEG 0:1:1 */
+ dev = pcidev_on_root(SA_DEV_SLOT_PEG, 1); /* PEG 0:1:1 */
if (!dev || !dev->enabled)
m_cfg->Peg1Enable = 0;
else if (dev->enabled) {
@@ -250,7 +250,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg,
m_t_cfg->Peg1Gen3EqPh3Method = 0;
}
- dev = SA_DEV_PEG2; /* PEG 0:1:2 */
+ dev = pcidev_on_root(SA_DEV_SLOT_PEG, 2); /* PEG 0:1:2 */
if (!dev || !dev->enabled)
m_cfg->Peg2Enable = 0;
else if (dev->enabled) {