diff options
Diffstat (limited to 'src/soc/intel/skylake/pmc.c')
| -rw-r--r-- | src/soc/intel/skylake/pmc.c | 43 |
1 files changed, 18 insertions, 25 deletions
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index e797b8f501..c2e724f353 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/io.h> #include <bootstate.h> #include <console/console.h> #include <device/mmio.h> @@ -8,7 +9,6 @@ #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> -#include <reg_script.h> #include <soc/pci_devs.h> #include <soc/pm.h> @@ -27,26 +27,6 @@ int pmc_soc_get_resources(struct pmc_resource_config *cfg) return 0; } -static const struct reg_script pch_pmc_misc_init_script[] = { - /* SLP_S4=4s, SLP_S3=50ms, disable SLP_X stretching after SUS loss. */ - REG_PCI_RMW16(GEN_PMCON_B, - ~(S4MAW_MASK | SLP_S3_MIN_ASST_WDTH_MASK), - S4MAW_4S | SLP_S3_MIN_ASST_WDTH_50MS | - DIS_SLP_X_STRCH_SUS_UP), - /* Enable SCI and clear SLP requests. */ - REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN), - REG_SCRIPT_END -}; - -static const struct reg_script pmc_write1_to_clear_script[] = { - REG_PCI_OR32(GEN_PMCON_A, 0), - REG_PCI_OR32(GEN_PMCON_B, 0), - REG_PCI_OR32(GEN_PMCON_B, 0), - REG_RES_OR32(PWRMBASE, GBLRST_CAUSE0, 0), - REG_RES_OR32(PWRMBASE, GBLRST_CAUSE1, 0), - REG_SCRIPT_END -}; - static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) { uint32_t reg; @@ -91,15 +71,24 @@ static void config_deep_sx(uint32_t deepsx_config) void pmc_soc_init(struct device *dev) { const config_t *config = config_of(dev); + uint8_t *const pwrmbase = pmc_mmio_regs(); + uint32_t reg32; rtc_init(); pmc_set_power_failure_state(true); pmc_gpe_init(); - /* Note that certain bits may be cleared from running script as - * certain bit fields are write 1 to clear. */ - reg_script_run_on_dev(dev, pch_pmc_misc_init_script); + /* SLP_S4=4s, SLP_S3=50ms, disable SLP_X stretching after SUS loss. */ + pci_update_config32(dev, GEN_PMCON_B, ~(S4MAW_MASK | SLP_S3_MIN_ASST_WDTH_MASK), + S4MAW_4S | SLP_S3_MIN_ASST_WDTH_50MS | DIS_SLP_X_STRCH_SUS_UP); + + /* Enable SCI and clear SLP requests. */ + reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); + reg32 &= ~SLP_TYP; + reg32 |= SCI_EN; + outl(reg32, ACPI_BASE_ADDRESS + PM1_CNT); + pmc_set_acpi_mode(); config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); @@ -107,7 +96,11 @@ void pmc_soc_init(struct device *dev) config_deep_sx(config->deep_sx_config); /* Clear registers that contain write-1-to-clear bits. */ - reg_script_run_on_dev(dev, pmc_write1_to_clear_script); + pci_or_config32(dev, GEN_PMCON_A, 0); + pci_or_config32(dev, GEN_PMCON_B, 0); + pci_or_config32(dev, GEN_PMCON_B, 0); + setbits32(pwrmbase + GBLRST_CAUSE0, 0); + setbits32(pwrmbase + GBLRST_CAUSE1, 0); } static void pm1_enable_pwrbtn_smi(void *unused) |