diff options
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/cpu.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/msr.h | 4 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 7bfd8bae2b..6419bf8506 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -51,6 +51,9 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 +/* Common Timer Copy (CTC) frequency - 19.2MHz. */ +#define CTC_FREQ 19200000 + #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index 98f25a153e..bb4b8e72ac 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -21,6 +21,10 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_BIOS_UPGD_TRIG 0x7a +#define MSR_EMULATE_PM_TIMER 0x121 +#define EMULATE_PM_TMR_EN (1 << 16) +#define EMULATE_DELAY_OFFSET_VALUE 20 +#define EMULATE_DELAY_VALUE 0x13 #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 |