3 files changed, 41 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h
index a7d9158ed5..321f04c5d3 100644
--- a/src/soc/intel/skylake/include/soc/gpio.h
+++ b/src/soc/intel/skylake/include/soc/gpio.h
@@ -43,6 +43,15 @@ void gpio_enable_all_smi(void);
 /* Enable GPIO individual Group SMI  */
 void gpio_enable_groupsmi(gpio_t gpio_num, u32 mask);
 
+/*
+ * Set the GPIO groups for the GPE blocks. The gpe0_route is interpreted
+ * as the packed configuration for GPE0_DW[2:0]:
+ *  dw0 = gpe0_route[3:0]
+ *  dw1 = gpe0_route[7:4]
+ *  dw2 = gpe0_route[11:8].
+ */
+void gpio_route_gpe(uint16_t gpe0_route);
+
 /* Configure the pads according to the pad_config array. */
 struct pad_config;
 void gpio_configure_pads(const struct pad_config *cfgs, size_t num);
diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h
index 625acdb74e..09f50199f6 100644
--- a/src/soc/intel/skylake/include/soc/gpio_defs.h
+++ b/src/soc/intel/skylake/include/soc/gpio_defs.h
@@ -21,6 +21,23 @@
 #define _SOC_GPIO_DEFS_H_
 
 /*
+ * There are 8 GPIO groups. GPP_A -> GPP_G and GPD. GPD is the special case
+ * where that group is not so generic. So most of the fixed numbers and macros
+ * are based on the GPP groups. The GPIO groups are accessed through register
+ * blocks called communities.
+ */
+#define GPP_A			0
+#define GPP_B			1
+#define GPP_C			2
+#define GPP_D			3
+#define GPP_E			4
+#define GPP_F			5
+#define GPP_G			6
+#define GPD			7
+#define GPIO_NUM_GROUPS		8
+#define GPIO_MAX_NUM_PER_GROUP	24
+
+/*
  * GPIOs are ordered monotonically increasing to match ACPI/OS driver.
  */
 
@@ -375,6 +392,12 @@
 #define GPD11_IRQ		0x5b
 
 /* Register defines. */
+#define MISCCFG_OFFSET		0x10
+#define  GPIO_DRIVER_IRQ_ROUTE_MASK	8
+#define  GPIO_DRIVER_IRQ_ROUTE_IRQ14	0
+#define  GPIO_DRIVER_IRQ_ROUTE_IRQ15	8
+#define  GPE_DW_SHIFT		8
+#define  GPE_DW_MASK		0xfff00
 #define PAD_OWN_REG_OFFSET	0x20
 #define  PAD_OWN_PADS_PER	8
 #define  PAD_OWN_WIDTH_PER	4
@@ -476,9 +499,9 @@
 #define  PAD_TERM_667_PU	13
 #define  PAD_TERM_NATIVE	15
 
-#define  MISCCFG_OFFSET			0x10
-#define  GPIO_DRIVER_IRQ_ROUTE_MASK	8
-#define  GPIO_DRIVER_IRQ_ROUTE_IRQ14	0
-#define  GPIO_DRIVER_IRQ_ROUTE_IRQ15	8
+#define GPI_GPE_STS_OFFSET	0x140
+#define GPI_GPE_EN_OFFSET	0x160
+#define GPI_SMI_STS_OFFSET	0x180
+#define GPI_SMI_EN_OFFSET	0x1a0
 
 #endif /* _SOC_GPIO_DEFS_H_ */
diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h
index 5774d46a4b..9c9b175285 100644
--- a/src/soc/intel/skylake/include/soc/pmc.h
+++ b/src/soc/intel/skylake/include/soc/pmc.h
@@ -91,6 +91,11 @@
 #define  DSX_EN_LAN_WAKE_PIN	(1 << 0)
 #define PMSYNC_TPR_CFG		0xc4
 #define  PMSYNC_LOCK		(1 << 31)
+#define GPIO_CFG		0x120
+#define  GPE0_DWX_MASK		0xf
+#define  GPE0_DW0_SHIFT		0
+#define  GPE0_DW1_SHIFT		4
+#define  GPE0_DW2_SHIFT		8
 #define GBLRST_CAUSE0		0x124
 #define GBLRST_CAUSE1		0x128