diff options
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pm.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/smbus.h | 14 |
2 files changed, 4 insertions, 13 deletions
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 47e3941531..f622edbde9 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -183,9 +183,6 @@ int acpi_sci_irq(void); /* Get base address PMC memory mapped registers. */ uint8_t *pmc_mmio_regs(void); -/* Get base address of TCO I/O registers. */ -uint16_t smbus_tco_regs(void); - /* Set the DISB after DRAM init */ void pmc_set_disb(void); diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h index aeaf1d9ea2..aad57aabb6 100644 --- a/src/soc/intel/skylake/include/soc/smbus.h +++ b/src/soc/intel/skylake/include/soc/smbus.h @@ -4,7 +4,7 @@ * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com> * Copyright (C) 2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. + * Copyright (C) 2015-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,20 +22,14 @@ /* PCI Configuration Space (D31:F3): SMBus */ #define SMB_RCV_SLVA 0x09 -/* SMBUS TCO base address. */ -#define TCOBASE 0x50 -#define TCOCTL 0x54 -#define TCO_EN (1 << 8) - /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 -#define TCO2_STS_SECOND_TO 0x02 -#define TCO2_STS_BOOT 0x04 +#define TCO_STS_SECOND_TO 0x02 #define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) +#define TCO_LOCK (1 << 12) +#define TCO_TMR_HLT (1 << 11) /* SMBus I/O bits. */ #define SMBUS_SLAVE_ADDR 0x24 |