diff options
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/bootblock.h | 6 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/p2sb.h | 28 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pcr.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/smbus.h | 12 |
4 files changed, 46 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index 10e1e03e22..e57c369d14 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -16,6 +16,12 @@ #ifndef _SOC_SKYLAKE_BOOTBLOCK_H_ #define _SOC_SKYLAKE_BOOTBLOCK_H_ +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#include <fsp/bootblock.h> +#else +inline void bootblock_fsp_temp_ram_init(void) {} +#endif + /* Bootblock pre console init programing */ void bootblock_cpu_init(void); void bootblock_pch_early_init(void); diff --git a/src/soc/intel/skylake/include/soc/p2sb.h b/src/soc/intel/skylake/include/soc/p2sb.h new file mode 100644 index 0000000000..354679f2a8 --- /dev/null +++ b/src/soc/intel/skylake/include/soc/p2sb.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_P2SB_H_ +#define _SOC_P2SB_H_ + +#define HPTC_OFFSET 0x60 +#define HPTC_ADDR_ENABLE_BIT (1 << 7) + +#define PCH_P2SB_EPMASK0 0xB0 +#define PCH_P2SB_EPMASK(mask_number) PCH_P2SB_EPMASK0 + (mask_number * 4) + +#define PCH_P2SB_E0 0xE0 +#define PCH_PWRM_ACPI_TMR_CTL 0xFC + +#endif /* _SOC_P2SB_H_ */ diff --git a/src/soc/intel/skylake/include/soc/pcr.h b/src/soc/intel/skylake/include/soc/pcr.h index c3e8d83a90..c83a26765a 100644 --- a/src/soc/intel/skylake/include/soc/pcr.h +++ b/src/soc/intel/skylake/include/soc/pcr.h @@ -35,6 +35,11 @@ #define B_PCH_PCR_DMI_GCS_BILD (1 << 0) #define R_PCH_PCR_DMI_LPCIOD 0x2770 #define R_PCH_PCR_DMI_LPCIOE 0x2774 +#define R_PCH_PCR_DMI_ACPIBA 0x27B4 +#define R_PCH_PCR_DMI_ACPIBDID 0x27B8 +#define R_PCH_PCR_DMI_PMBASEA 0x27AC +#define R_PCH_PCR_DMI_PMBASEC 0x27B0 +#define R_PCH_PCR_DMI_TCOBASE 0x2778 /* RTC configuration */ #define R_PCH_PCR_RTC_CONF 0x3400 diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h index ff89f3ab28..856b4a9d63 100644 --- a/src/soc/intel/skylake/include/soc/smbus.h +++ b/src/soc/intel/skylake/include/soc/smbus.h @@ -22,19 +22,21 @@ /* PCI Configuration Space (D31:F3): SMBus */ #define SMB_BASE 0x20 #define HOSTC 0x40 -#define HST_EN (1 << 0) +#define HST_EN (1 << 0) #define SMB_RCV_SLVA 0x09 /* SMBUS TCO base address. */ #define TCOBASE 0x50 +#define TCOCTL 0x54 +#define SMBUS_TCO_EN (1 << 8) /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ #define TCO1_STS 0x04 #define TCO2_STS 0x06 -#define TCO2_STS_SECOND_TO 0x02 -#define TCO2_STS_BOOT 0x04 +#define TCO2_STS_SECOND_TO 0x02 +#define TCO2_STS_BOOT 0x04 #define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) +#define TCO_LOCK (1 << 12) +#define TCO_TMR_HLT (1 << 11) /* SMBus I/O bits. */ #define SMBHSTSTAT 0x0 |