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-rw-r--r--src/soc/intel/skylake/include/soc/nvs.h4
-rw-r--r--src/soc/intel/skylake/include/soc/usb.h7
2 files changed, 10 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index f9d5b71880..cb3b2c6ee5 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -54,7 +54,9 @@ typedef struct {
u64 nhla; /* 0x31 - NHLT Address */
u32 nhll; /* 0x39 - NHLT Length */
u16 cid1; /* 0x3d - Wifi Country Identifier */
- u8 unused[193];
+ u16 u2we; /* 0x3f - USB2 Wake Enable Bitmap */
+ u8 u3we; /* 0x41 - USB3 Wake Enable Bitmap */
+ u8 unused[190];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
diff --git a/src/soc/intel/skylake/include/soc/usb.h b/src/soc/intel/skylake/include/soc/usb.h
index e5b0495f05..a18e79ce66 100644
--- a/src/soc/intel/skylake/include/soc/usb.h
+++ b/src/soc/intel/skylake/include/soc/usb.h
@@ -169,4 +169,11 @@ struct usb3_port_config {
.tx_downscale_amp = 0x00, \
}
+/*
+ * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds
+ * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to
+ * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits.
+ */
+#define USB_PORT_WAKE_ENABLE(x) (1 << (x - 1))
+
#endif