diff options
Diffstat (limited to 'src/soc/intel/skylake/chip.c')
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 65 |
1 files changed, 51 insertions, 14 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 00261522ce..f1a104c879 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,15 +15,16 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ +#include <chip.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> +#include <fsp_util.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> -#include <soc/intel/broadwell/chip.h> static void pci_domain_set_resources(device_t dev) { @@ -36,14 +38,20 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = &pci_bus_default_ops, }; +static void chip_final(device_t dev) +{ + /* Notify FSP done device setup */ + printk(BIOS_DEBUG, + "Calling FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); + fsp_notify(EnumInitPhaseAfterPciEnumeration); +} + static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = &broadwell_init_cpus, + .init = &soc_init_cpus, + .final = &chip_final, }; -static void broadwell_enable(device_t dev) +static void soc_enable(device_t dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { @@ -52,19 +60,48 @@ static void broadwell_enable(device_t dev) dev->ops = &cpu_bus_ops; } else if (dev->path.type == DEVICE_PATH_PCI) { /* Handle PCH device enable */ - if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_MINIHD && + if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_IGD && (dev->ops == NULL || dev->ops->enable == NULL)) { - broadwell_pch_enable_dev(dev); + pch_enable_dev(dev); } } } -struct chip_operations soc_intel_broadwell_ops = { - CHIP_NAME("Intel Broadwell") - .enable_dev = &broadwell_enable, - .init = &broadwell_init_pre_device, +struct chip_operations soc_intel_skylake_ops = { + CHIP_NAME("Intel Skylake") + .enable_dev = &soc_enable, + .init = &soc_init_pre_device, }; +/* UPD parameters to be initialized before SiliconInit */ +void soc_silicon_init_params(SILICON_INIT_UPD *params) +{ + const struct device *dev; + const struct soc_intel_skylake_config *config; + + /* Set the parameters for SiliconInit */ + dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); + if (!dev || !dev->chip_info) + return; + config = dev->chip_info; + + params->Device4Enable = config->Device4Enable; +} + +void soc_display_silicon_init_params(const SILICON_INIT_UPD *original, + SILICON_INIT_UPD *params) +{ + /* Display the parameters for SiliconInit */ + printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); + + soc_display_upd_value("GpioTablePtr", 4, + (uint32_t)original->GpioTablePtr, + (uint32_t)params->GpioTablePtr); + soc_display_upd_value("Device4Enable", 1, + original->Device4Enable, + params->Device4Enable); +} + static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { if (!vendor || !device) @@ -75,6 +112,6 @@ static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) (device << 16) | vendor); } -struct pci_operations broadwell_pci_ops = { +struct pci_operations soc_pci_ops = { .set_subsystem = &pci_set_subsystem }; |