2 files changed, 15 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
index ab1720c83a..f644d1f638 100644
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ b/src/soc/intel/skylake/bootblock/bootblock.c
@@ -14,7 +14,6 @@
  */
 
 #include <bootblock_common.h>
-#include <fsp/bootblock.h>
 #include <soc/bootblock.h>
 #include <soc/romstage.h>
 
@@ -36,12 +35,14 @@ void bootblock_soc_early_init(void)
 
 void bootblock_soc_init(void)
 {
-	/* locate and call FspTempRamInit */
-	bootblock_fsp_temp_ram_init();
+	/* FSP 2.0 does not provide FSP-T/TempRamInit init support yet */
+	if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1))
+		bootblock_fsp_temp_ram_init();
+
 	/*
 	 * Perform early chipset initialization before fsp memory init
-	 * example: pirq->irq programming, enabling smbus, pmcbase, abase,
-	 * 			get platform info, i2c programming
+	 * example: pirq->irq programming, enabling smbus, set pmcbase
+	 * and abase, i2c programming and print platform info
 	 */
 	report_platform_info();
 	set_max_freq();
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 569611502e..e7f414b721 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -18,6 +18,7 @@
 #include <soc/bootblock.h>
 #include <soc/iomap.h>
 #include <soc/lpc.h>
+#include <soc/p2sb.h>
 #include <soc/pci_devs.h>
 #include <soc/pcr.h>
 #include <soc/spi.h>
@@ -64,6 +65,14 @@ static void enable_p2sbbar(void)
 	/* Enable P2SB MSE */
 	pci_write_config8(dev, PCI_COMMAND,
 			  PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+
+	/*
+	 * Enable decoding for HPET memory address range.
+	 * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
+	 * the High Performance Timer memory address range
+	 * selected by bits 1:0
+	 */
+	pci_write_config8(dev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT);
 }
 
 void bootblock_pch_early_init(void)