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path: root/src/soc/intel/skylake/bootblock/pch.c
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Diffstat (limited to 'src/soc/intel/skylake/bootblock/pch.c')
-rw-r--r--src/soc/intel/skylake/bootblock/pch.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 6279cf2b6d..07beae8f9e 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -192,8 +192,8 @@ static void soc_config_pwrmbase(void)
*
* Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16]
* to the value programmed in PMC PCI Offset 48h bit[31:16], this has an
- * implication of making sure the memory allocated to PWRMBASE to be 64KB
- * in size.
+ * implication of making sure the memory allocated to PWRMBASE to be
+ * 64KB in size.
*/
pcr_write32(PID_DMI, R_PCH_PCR_DMI_PMBASEA,
((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) |