aboutsummaryrefslogtreecommitdiff
path: root/src/soc/intel/skylake/bootblock/pch.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/intel/skylake/bootblock/pch.c')
-rw-r--r--src/soc/intel/skylake/bootblock/pch.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 569611502e..e7f414b721 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -18,6 +18,7 @@
#include <soc/bootblock.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
+#include <soc/p2sb.h>
#include <soc/pci_devs.h>
#include <soc/pcr.h>
#include <soc/spi.h>
@@ -64,6 +65,14 @@ static void enable_p2sbbar(void)
/* Enable P2SB MSE */
pci_write_config8(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+
+ /*
+ * Enable decoding for HPET memory address range.
+ * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
+ * the High Performance Timer memory address range
+ * selected by bits 1:0
+ */
+ pci_write_config8(dev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT);
}
void bootblock_pch_early_init(void)