diff options
Diffstat (limited to 'src/soc/intel/skylake/acpi')
22 files changed, 1168 insertions, 1005 deletions
diff --git a/src/soc/intel/skylake/acpi/adsp.asl b/src/soc/intel/skylake/acpi/adsp.asl deleted file mode 100644 index cb10d9a9ad..0000000000 --- a/src/soc/intel/skylake/acpi/adsp.asl +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -Device (ADSP) -{ - Method (_HID, 0, Serialized) - { - If (\ISWP ()) { - // WildcatPoint - Return ("INT3438") - } - - // LynxPoint-LP - Return ("INT33C8") - } - Name (_UID, 1) - Name (_DDN, "Intel Smart Sound Technology") - - Name (RBUF, ResourceTemplate () - { - Memory32Fixed (ReadWrite, 0x00000000, 0x00100000, BAR0) - Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR1) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {3} - }) - - Method (_CRS, 0, NotSerialized) - { - // Update BAR address and length if set in NVS - If (LNotEqual (\S8B0, Zero)) { - CreateDwordField (^RBUF, ^BAR0._BAS, B8A0) - CreateDwordField (^RBUF, ^BAR1._BAS, B8A1) - Store (\S8B0, B8A0) - Store (\S8B1, B8A1) - } - - Return (RBUF) - } - - Method (_STA, 0, NotSerialized) - { - If (LEqual (\S8EN, 0)) { - Return (0x0) - } Else { - Return (0xF) - } - } - - Device (I2S0) - { - Name (_ADR, 0) - } - - Device (I2S1) - { - Name (_ADR, 1) - } -} diff --git a/src/soc/intel/skylake/acpi/cpu.asl b/src/soc/intel/skylake/acpi/cpu.asl index 2921ceae5e..5856033862 100644 --- a/src/soc/intel/skylake/acpi/cpu.asl +++ b/src/soc/intel/skylake/acpi/cpu.asl @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ /* These devices are created at runtime */ diff --git a/src/soc/intel/skylake/acpi/ctdp.asl b/src/soc/intel/skylake/acpi/ctdp.asl index a2a8fb4d2c..1668b4cfaa 100644 --- a/src/soc/intel/skylake/acpi/ctdp.asl +++ b/src/soc/intel/skylake/acpi/ctdp.asl @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ Scope (\_SB.PCI0.MCHC) @@ -30,40 +31,43 @@ Scope (\_SB.PCI0.MCHC) Add (MCH_BASE_ADDRESS, 0x5000), 0x1000) Field (MCHB, DWordAcc, Lock, Preserve) { - Offset (0x930), /* PACKAGE_POWER_SKU */ + Offset (0x930), /* PACKAGE_POWER_SKU */ CTDN, 15, /* CTDP Nominal PL1 */ - Offset (0x938), /* PACKAGE_POWER_SKU_UNIT */ + Offset (0x938), /* PACKAGE_POWER_SKU_UNIT */ PUNI, 4, /* Power Units */ , 4, EUNI, 5, /* Energy Units */ , 3, TUNI, 4, /* Time Units */ - Offset (0x958), /* PLATFORM_INFO */ - , 40, + Offset (0x958), /* PLATFORM_INFO */ + , 32, + LPMS, 1, /* LPM Support */ + CTNL, 2, /* Config TDP Number level */ + , 5, LFM_, 8, /* Maximum Efficiency Ratio (LFM) */ - Offset (0x9a0), /* TURBO_POWER_LIMIT1 */ + Offset (0x9a0), /* TURBO_POWER_LIMIT1 */ PL1V, 15, /* Power Limit 1 Value */ PL1E, 1, /* Power Limit 1 Enable */ PL1C, 1, /* Power Limit 1 Clamp */ PL1T, 7, /* Power Limit 1 Time */ - Offset (0x9a4), /* TURBO_POWER_LIMIT2 */ + Offset (0x9a4), /* TURBO_POWER_LIMIT2 */ PL2V, 15, /* Power Limit 2 Value */ PL2E, 1, /* Power Limit 2 Enable */ PL2C, 1, /* Power Limit 2 Clamp */ PL2T, 7, /* Power Limit 2 Time */ - Offset (0xf3c), /* CONFIG_TDP_NOMINAL */ + Offset (0xf3c), /* CONFIG_TDP_NOMINAL */ TARN, 8, /* CTDP Nominal Turbo Activation Ratio */ - Offset (0xf40), /* CONFIG_TDP_LEVEL1 */ + Offset (0xf40), /* CONFIG_TDP_LEVEL1 */ CTDD, 15, /* CTDP Down PL1 */ , 1, TARD, 8, /* CTDP Down Turbo Activation Ratio */ - Offset (0xf48), /* MSR_CONFIG_TDP_LEVEL2 */ + Offset (0xf48), /* MSR_CONFIG_TDP_LEVEL2 */ CTDU, 15, /* CTDP Up PL1 */ , 1, TARU, 8, /* CTDP Up Turbo Activation Ratio */ - Offset (0xf50), /* CONFIG_TDP_CONTROL */ + Offset (0xf50), /* CONFIG_TDP_CONTROL */ CTCS, 2, /* CTDP Select */ - Offset (0xf54), /* TURBO_ACTIVATION_RATIO */ + Offset (0xf54), /* TURBO_ACTIVATION_RATIO */ TARS, 8, /* Turbo Activation Ratio Select */ } @@ -85,7 +89,7 @@ Scope (\_SB.PCI0.MCHC) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) + (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } @@ -98,8 +102,6 @@ Scope (\_SB.PCI0.MCHC) /* Calculate PL2 based on chip type */ Method (CPL2, 1, NotSerialized) { - /* Haswell ULT PL2 = 25W */ - /* FIXME: update for broadwell */ Return (Multiply (25, 8)) } diff --git a/src/soc/intel/skylake/acpi/device_nvs.asl b/src/soc/intel/skylake/acpi/device_nvs.asl index 1d2aa78edb..e84d25ae9b 100644 --- a/src/soc/intel/skylake/acpi/device_nvs.asl +++ b/src/soc/intel/skylake/acpi/device_nvs.asl @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,41 +15,46 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ /* Device Enabled in ACPI Mode */ -S0EN, 8, // DMA Enable -S1EN, 8, // I2C0 Enable -S2EN, 8, // I2C1 Enable -S3EN, 8, // SPI0 Enable -S4EN, 8, // SPI1 Enable -S5EN, 8, // UART0 Enable -S6EN, 8, // UART1 Enable -S7EN, 8, // SDIO Enable -S8EN, 8, // ADSP Enable +S0EN, 8, // I2C0 Enable +S1EN, 8, // I2C1 Enable +S2EN, 8, // I2C2 Enable +S3EN, 8, // I2C3 Enable +S4EN, 8, // I2C4 Enable +S5EN, 8, // I2C5 Enable +S6EN, 8, // SPI0 Enable +S7EN, 8, // SPI1 Enable +S8EN, 8, // UART0 Enable +S9EN, 8, // UART1 Enable +SAEN, 8, // UART2 Enable /* BAR 0 */ - -S0B0, 32, // DMA BAR0 -S1B0, 32, // I2C0 BAR0 -S2B0, 32, // I2C1 BAR0 -S3B0, 32, // SPI0 BAR0 -S4B0, 32, // SPI1 BAR0 -S5B0, 32, // UART0 BAR0 -S6B0, 32, // UART1 BAR0 -S7B0, 32, // SDIO BAR0 -S8B0, 32, // ADSP BAR0 +S0B0, 32, // I2C0 BAR0 +S1B0, 32, // I2C1 BAR0 +S2B0, 32, // I2C2 BAR0 +S3B0, 32, // I2C3 BAR0 +S4B0, 32, // I2C4 BAR0 +S5B0, 32, // I2C5 BAR0 +S6B0, 32, // SPI0 BAR0 +S7B0, 32, // SPI1 BAR0 +S8B0, 32, // UART0 BAR0 +S9B0, 32, // UART1 BAR0 +SAB0, 32, // UART2 BAR0 /* BAR 1 */ +S0B1, 32, // I2C0 BAR1 +S1B1, 32, // I2C1 BAR1 +S2B1, 32, // I2C2 BAR1 +S3B1, 32, // I2C3 BAR1 +S4B1, 32, // I2C4 BAR1 +S5B1, 32, // I2C5 BAR1 +S6B1, 32, // SPI0 BAR1 +S7B1, 32, // SPI1 BAR1 +S8B1, 32, // UART0 BAR1 +S9B1, 32, // UART1 BAR1 +SAB1, 32, // UART2 BAR1 -S0B1, 32, // DMA BAR1 -S1B1, 32, // I2C0 BAR1 -S2B1, 32, // I2C1 BAR1 -S3B1, 32, // SPI0 BAR1 -S4B1, 32, // SPI1 BAR1 -S5B1, 32, // UART0 BAR1 -S6B1, 32, // UART1 BAR1 -S7B1, 32, // SDIO BAR1 -S8B1, 32, // ADSP BAR1 diff --git a/src/soc/intel/skylake/acpi/ehci.asl b/src/soc/intel/skylake/acpi/ehci.asl deleted file mode 100644 index a2e704fccf..0000000000 --- a/src/soc/intel/skylake/acpi/ehci.asl +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -// EHCI Controller 0:1d.0 - -Device (EHCI) -{ - Name(_ADR, 0x001d0000) - Name (_PRW, Package(){ 0x6d, 3 }) - - // Leave USB ports on for to allow Wake from USB - - Method(_S3D,0) // Highest D State in S3 State - { - Return (2) - } - - Method(_S4D,0) // Highest D State in S4 State - { - Return (2) - } - - Device (HUB7) - { - Name (_ADR, 0x00000000) - - // How many are there? - Device (PRT1) { Name (_ADR, 1) } // USB Port 0 - Device (PRT2) { Name (_ADR, 2) } // USB Port 1 - Device (PRT3) { Name (_ADR, 3) } // USB Port 2 - Device (PRT4) { Name (_ADR, 4) } // USB Port 3 - Device (PRT5) { Name (_ADR, 5) } // USB Port 4 - Device (PRT6) { Name (_ADR, 6) } // USB Port 5 - } -} diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index 223d21a676..3df40cd946 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -3,6 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,7 +16,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ /* Global Variables */ @@ -29,8 +30,7 @@ Name (\PICM, 0) // IOAPIC/8259 * we have to fix it up in coreboot's ACPI creation phase. */ -External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) +OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x2000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -62,6 +62,18 @@ Field (GNVS, ByteAcc, NoLock, Preserve) CBMC, 32, // 0x1c - 0x1f - Coreboot Memory Console PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit GPEI, 64, // 0x28 - 0x2f - GPE wake status bit + RPA1, 32, // 0x30 - 0x33 - Root port address 1 + RPA2, 32, // 0x34 - 0x37 - Root port address 2 + RPA3, 32, // 0x38 - 0x3b - Root port address 3 + RPA4, 32, // 0x3c - 0x3f - Root port address 4 + RPA5, 32, // 0x40 - 0x43 - Root port address 5 + RPA6, 32, // 0x44 - 0x47 - Root port address 6 + RPA7, 32, // 0x48 - 0x4b - Root port address 7 + RPA8, 32, // 0x4c - 0x4f - Root port address 8 + RPA9, 32, // 0x50 - 0x53 - Root port address 9 + RPAA, 32, // 0x54 - 0x57 - Root port address 10 + RPAB, 32, // 0x58 - 0x5b - Root port address 11 + RPAC, 32, // 0x5c - 0x5f - Root port address 12 /* ChromeOS specific */ Offset (0x100), @@ -72,18 +84,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) #include "device_nvs.asl" } -/* Set flag to enable USB charging in S3 */ -Method (S3UE) -{ - Store (One, \S3U0) -} - -/* Set flag to disable USB charging in S3 */ -Method (S3UD) -{ - Store (Zero, \S3U0) -} - /* Set flag to enable USB charging in S5 */ Method (S5UE) { @@ -95,15 +95,3 @@ Method (S5UD) { Store (Zero, \S5U0) } - -/* Set flag to enable 3G module in S3 */ -Method (S3GE) -{ - Store (One, \S33G) -} - -/* Set flag to disable 3G module in S3 */ -Method (S3GD) -{ - Store (Zero, \S33G) -} diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl index c6d8753975..69ee721393 100644 --- a/src/soc/intel/skylake/acpi/gpio.asl +++ b/src/soc/intel/skylake/acpi/gpio.asl @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ Device (GPIO) @@ -22,13 +23,8 @@ Device (GPIO) // GPIO Controller Method (_HID) { - If (\ISWP ()) { - // WildcatPoint - Return ("INT3437") - } - - // LynxPoint-LP - Return ("INT33C7") + //Sunrisepoint-LP PCH + Return ("INT344B") } Name (_UID, 1) diff --git a/src/soc/intel/skylake/acpi/hda.asl b/src/soc/intel/skylake/acpi/hda.asl deleted file mode 100644 index 21736615ac..0000000000 --- a/src/soc/intel/skylake/acpi/hda.asl +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Intel PCH HDA */ - -// Intel High Definition Audio (Azalia) 0:1b.0 - -Device (HDEF) -{ - Name (_ADR, 0x001b0000) - Name (_PRW, Package () { 0x6d, 3 }) -} diff --git a/src/soc/intel/skylake/acpi/irqlinks.asl b/src/soc/intel/skylake/acpi/irqlinks.asl index ba550e2a46..1f6e62352c 100644 --- a/src/soc/intel/skylake/acpi/irqlinks.asl +++ b/src/soc/intel/skylake/acpi/irqlinks.asl @@ -3,6 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,7 +16,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ Device (LNKA) @@ -26,14 +27,14 @@ Device (LNKA) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTA) + Or (\_SB.PARC, 0x80, \_SB.PARC) } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 3, 4, 5, 6, 10, 12, 14, 15 } }) // Current Resource Settings for this link @@ -49,7 +50,7 @@ Device (LNKA) Store (Zero, IRQ0) // Set the bit from PRTA - ShiftLeft (1, And (PRTA, 0x0f), IRQ0) + ShiftLeft (1, And (\_SB.PARC, 0x0f), IRQ0) Return (RTLA) } @@ -63,13 +64,13 @@ Device (LNKA) FindSetRightBit (IRQ0, Local0) Decrement(Local0) - Store (Local0, PRTA) + Store (Local0, \_SB.PARC) } // Status Method (_STA, 0, Serialized) { - If(And (PRTA, 0x80)) { + If(And (\_SB.PARC, 0x80)) { Return (0x9) } Else { Return (0xb) @@ -85,14 +86,14 @@ Device (LNKB) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTB) + Or (\_SB.PBRC, 0x80, \_SB.PBRC) } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 3, 4, 5, 6, 10, 12, 14, 15 } }) // Current Resource Settings for this link @@ -108,7 +109,7 @@ Device (LNKB) Store (Zero, IRQ0) // Set the bit from PRTB - ShiftLeft (1, And (PRTB, 0x0f), IRQ0) + ShiftLeft (1, And (\_SB.PBRC, 0x0f), IRQ0) Return (RTLB) } @@ -122,13 +123,13 @@ Device (LNKB) FindSetRightBit (IRQ0, Local0) Decrement(Local0) - Store (Local0, PRTB) + Store (Local0, \_SB.PBRC) } // Status Method (_STA, 0, Serialized) { - If(And (PRTB, 0x80)) { + If(And (\_SB.PBRC, 0x80)) { Return (0x9) } Else { Return (0xb) @@ -144,14 +145,14 @@ Device (LNKC) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTC) + Or (\_SB.PCRC, 0x80, \_SB.PCRC) } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 3, 4, 5, 6, 10, 12, 14, 15 } }) // Current Resource Settings for this link @@ -167,7 +168,7 @@ Device (LNKC) Store (Zero, IRQ0) // Set the bit from PRTC - ShiftLeft (1, And (PRTC, 0x0f), IRQ0) + ShiftLeft (1, And (\_SB.PCRC, 0x0f), IRQ0) Return (RTLC) } @@ -181,13 +182,13 @@ Device (LNKC) FindSetRightBit (IRQ0, Local0) Decrement(Local0) - Store (Local0, PRTC) + Store (Local0, \_SB.PCRC) } // Status Method (_STA, 0, Serialized) { - If(And (PRTC, 0x80)) { + If(And (\_SB.PCRC, 0x80)) { Return (0x9) } Else { Return (0xb) @@ -203,14 +204,14 @@ Device (LNKD) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTD) + Or (\_SB.PDRC, 0x80, \_SB.PDRC) } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 3, 4, 5, 6, 10, 12, 14, 15 } }) // Current Resource Settings for this link @@ -226,7 +227,7 @@ Device (LNKD) Store (Zero, IRQ0) // Set the bit from PRTD - ShiftLeft (1, And (PRTD, 0x0f), IRQ0) + ShiftLeft (1, And (\_SB.PDRC, 0x0f), IRQ0) Return (RTLD) } @@ -240,13 +241,13 @@ Device (LNKD) FindSetRightBit (IRQ0, Local0) Decrement(Local0) - Store (Local0, PRTD) + Store (Local0, \_SB.PDRC) } // Status Method (_STA, 0, Serialized) { - If(And (PRTD, 0x80)) { + If(And (\_SB.PDRC, 0x80)) { Return (0x9) } Else { Return (0xb) @@ -262,14 +263,14 @@ Device (LNKE) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTE) + Or (\_SB.PERC, 0x80, \_SB.PERC) } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 3, 4, 5, 6, 10, 12, 14, 15 } }) // Current Resource Settings for this link @@ -285,7 +286,7 @@ Device (LNKE) Store (Zero, IRQ0) // Set the bit from PRTE - ShiftLeft (1, And (PRTE, 0x0f), IRQ0) + ShiftLeft (1, And (\_SB.PERC, 0x0f), IRQ0) Return (RTLE) } @@ -299,13 +300,13 @@ Device (LNKE) FindSetRightBit (IRQ0, Local0) Decrement(Local0) - Store (Local0, PRTE) + Store (Local0, \_SB.PERC) } // Status Method (_STA, 0, Serialized) { - If(And (PRTE, 0x80)) { + If(And (\_SB.PERC, 0x80)) { Return (0x9) } Else { Return (0xb) @@ -321,14 +322,14 @@ Device (LNKF) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTF) + Or (\_SB.PFRC, 0x80, \_SB.PFRC) } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 3, 4, 5, 6, 10, 12, 14, 15 } }) // Current Resource Settings for this link @@ -344,7 +345,7 @@ Device (LNKF) Store (Zero, IRQ0) // Set the bit from PRTF - ShiftLeft (1, And (PRTF, 0x0f), IRQ0) + ShiftLeft (1, And (\_SB.PFRC, 0x0f), IRQ0) Return (RTLF) } @@ -358,13 +359,13 @@ Device (LNKF) FindSetRightBit (IRQ0, Local0) Decrement(Local0) - Store (Local0, PRTF) + Store (Local0, \_SB.PFRC) } // Status Method (_STA, 0, Serialized) { - If(And (PRTF, 0x80)) { + If(And (\_SB.PFRC, 0x80)) { Return (0x9) } Else { Return (0xb) @@ -380,14 +381,14 @@ Device (LNKG) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTG) + Or (\_SB.PGRC, 0x80, \_SB.PGRC) } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 3, 4, 5, 6, 10, 12, 14, 15 } }) // Current Resource Settings for this link @@ -403,7 +404,7 @@ Device (LNKG) Store (Zero, IRQ0) // Set the bit from PRTG - ShiftLeft (1, And (PRTG, 0x0f), IRQ0) + ShiftLeft (1, And (\_SB.PGRC, 0x0f), IRQ0) Return (RTLG) } @@ -417,13 +418,13 @@ Device (LNKG) FindSetRightBit (IRQ0, Local0) Decrement(Local0) - Store (Local0, PRTG) + Store (Local0, \_SB.PGRC) } // Status Method (_STA, 0, Serialized) { - If(And (PRTG, 0x80)) { + If(And (\_SB.PGRC, 0x80)) { Return (0x9) } Else { Return (0xb) @@ -439,14 +440,14 @@ Device (LNKH) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTH) + Or (\_SB.PHRC, 0x80, \_SB.PHRC) } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 3, 4, 5, 6, 10, 12, 14, 15 } }) // Current Resource Settings for this link @@ -462,7 +463,7 @@ Device (LNKH) Store (Zero, IRQ0) // Set the bit from PRTH - ShiftLeft (1, And (PRTH, 0x0f), IRQ0) + ShiftLeft (1, And (\_SB.PHRC, 0x0f), IRQ0) Return (RTLH) } @@ -476,13 +477,13 @@ Device (LNKH) FindSetRightBit (IRQ0, Local0) Decrement(Local0) - Store (Local0, PRTH) + Store (Local0, \_SB.PHRC) } // Status Method (_STA, 0, Serialized) { - If(And (PRTH, 0x80)) { + If(And (\_SB.PHRC, 0x80)) { Return (0x9) } Else { Return (0xb) diff --git a/src/soc/intel/skylake/acpi/itss.asl b/src/soc/intel/skylake/acpi/itss.asl new file mode 100644 index 0000000000..8ba9513abd --- /dev/null +++ b/src/soc/intel/skylake/acpi/itss.asl @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* ITSS */ +/* Define the needed ITSS registers used by ASL on Interrupt */ + +Scope (\_SB) +{ + OperationRegion (ITSS, SystemMemory, 0xfdc43100, 0x8) + Field (ITSS, ByteAcc, NoLock, Preserve) + { + PARC, 8, + PBRC, 8, + PCRC, 8, + PDRC, 8, + PERC, 8, + PFRC, 8, + PGRC, 8, + PHRC, 8, + } + + /* + * Pin# = group_pad# + group# * 24. + * For instance, GPP_A_6 would be pin#6, + * GPP_D_23 would be 23+(3*24), pin#95. + */ + Name (GPPG, Package (0x02) + { + Package (0x08) + { + 0x18, + 0x18, + 0x18, + 0x18, + 0x18, + 0x18, + 0x08, + 0x0C + }, + + Package (0x0A) + { + 0x18, + 0x18, + 0x18, + 0x18, + 0x0D, + 0x18, + 0x18, + 0x18, + 0x0B, + 0x0C + } + }) + + Method (GNMB, 1, Serialized) + { + Return (And (Arg0, 0xFFFF)) + } + + Method (GGRP, 1, Serialized) + { + ShiftRight (And (Arg0, 0x00FF0000), 0x10, Local0) + Return (Local0) + } + + /* Convert GPIO PAD name to GPIO number */ + Method (INUM, 1, NotSerialized) + { + Store (One, Local0) + Store (GNMB (Arg0), Local1) + Store (GGRP (Arg0), Local2) + Store (Zero, Local3) + + While (LLess (Local3, Local2)) + { + Add (DerefOf (Index (DerefOf (Index + (GPPG, Local0)), Local3)), + Local1, Local1) + Increment (Local3) + } + + Return (Add (0x18, Mod (Local1, 0x60))) + } +} diff --git a/src/soc/intel/skylake/acpi/lpc.asl b/src/soc/intel/skylake/acpi/lpc.asl index 2b574f756d..8332980730 100644 --- a/src/soc/intel/skylake/acpi/lpc.asl +++ b/src/soc/intel/skylake/acpi/lpc.asl @@ -3,6 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,9 +16,11 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ +#include <soc/iomap.h> + // Intel LPC Bus Device - 0:1f.0 Device (LPCB) @@ -33,16 +36,7 @@ Device (LPCB) PMBS, 16, // PMBASE Offset (0x48), GPBS, 16, // GPIOBASE - Offset (0x60), // Interrupt Routing Registers - PRTA, 8, - PRTB, 8, - PRTC, 8, - PRTD, 8, - Offset (0x68), - PRTE, 8, - PRTF, 8, - PRTG, 8, - PRTH, 8, + Offset (0x80), // IO Decode Ranges IOD0, 8, @@ -74,48 +68,22 @@ Device (LPCB) Device (HPET) { Name (_HID, EISAID("PNP0103")) - Name (_CID, 0x010CD041) - Name (BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status { - If (HPTE) { - // Note: Ancient versions of Windows don't want - // to see the HPET in order to work right - If (LGreaterEqual(OSYS, 2001)) { - Return (0xf) // Enable and show device - } Else { - Return (0xb) // Enable and don't show device - } - } - - Return (0x0) // Not enabled, don't show. + Return (0xf) } - Method (_CRS, 0, Serialized) // Current resources { - If (HPTE) { - CreateDWordField (BUF0, - \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) - - If (Lequal(HPAS, 1)) { - Store(0xfed01000, HPT0) - } - - If (Lequal(HPAS, 2)) { - Store(0xfed02000, HPT0) - } - - If (Lequal(HPAS, 3)) { - Store(0xfed03000, HPT0) - } - } + CreateDWordField (BUF0, ^FED0._BAS, HPT0) + /* TODO: Base address configured need to pass as GNVS */ + Store(HPET_BASE_ADDRESS, HPT0) - Return (BUF0) + Return(BUF0) } } diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 998133d9d9..2621eb287d 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -3,6 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,78 +16,47 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <soc/iomap.h> Scope (\) { - // IO-Trap at 0x800. This is the ACPI->SMI communication interface. + /* IO-Trap at 0x800. + * This is the ACPI->SMI communication interface. + */ OperationRegion (IO_T, SystemIO, 0x800, 0x10) Field (IO_T, ByteAcc, NoLock, Preserve) { Offset (0x8), - TRP0, 8 // IO-Trap at 0x808 - } - - // Root Complex Register Block - OperationRegion (RCRB, SystemMemory, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) - Field (RCRB, DWordAcc, Lock, Preserve) - { - Offset (0x3404), // High Performance Timer Configuration - HPAS, 2, // Address Select - , 5, - HPTE, 1, // Address Enable - } - - /* - * Check PCH type - * Return 1 if PCH is WildcatPoint - * Return 0 if PCH is LynxPoint - */ - Method (ISWP) - { - And (\_SB.PCI0.LPCB.PDID, 0xfff0, Local0) - If (LEqual (Local0, 0x9cc0)) { - Return (1) - } Else { - Return (0) - } + TRP0, 8 /* IO-Trap at 0x808 */ } } -// High Definition Audio (Azalia) 0:1b.0 -#include "hda.asl" - -// ADSP/SST 0:13.0 -#include "adsp.asl" - -// PCI Express Ports 0:1c.x +/* PCI Express Ports 0:1c.x */ #include "pcie.asl" -// USB EHCI 0:1d.0 -#include "ehci.asl" - -// USB XHCI 0:14.0 +/* USB XHCI 0:14.0 */ #include "xhci.asl" -// LPC Bridge 0:1f.0 +/* LPC Bridge 0:1f.0 */ #include "lpc.asl" -// SATA 0:1f.2 -#include "sata.asl" - -// SMBus 0:1f.3 +/* SMBus 0:1f.3 */ #include "smbus.asl" -// Serial IO +/* Serial IO */ #include "serialio.asl" +/* Interrupt Routing */ +#include "itss.asl" +#include "irqlinks.asl" + Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (LEqual (Arg0, ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { /* Let OS control everything */ Return (Arg3) diff --git a/src/soc/intel/skylake/acpi/pci_irqs.asl b/src/soc/intel/skylake/acpi/pci_irqs.asl index 0c23e10a51..c43e42dbb6 100644 --- a/src/soc/intel/skylake/acpi/pci_irqs.asl +++ b/src/soc/intel/skylake/acpi/pci_irqs.asl @@ -3,6 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,74 +16,127 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ Method(_PRT) { If (PICM) { Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // Audio DSP (Smart Sound) 0:13.0 - Package() { 0x0013ffff, 0, 0, 23 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 18 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 22 }, - Package() { 0x001fffff, 1, 0, 18 }, - Package() { 0x001fffff, 2, 0, 17 }, - Package() { 0x001fffff, 3, 0, 16 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, 0, 20 }, - Package() { 0x0015ffff, 1, 0, 21 }, - Package() { 0x0015ffff, 2, 0, 21 }, - Package() { 0x0015ffff, 3, 0, 21 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, 0, 23 }, + /* PCI Bridge */ + /* D31: cAVS, SMBus, GbE, Nothpeak */ + Package(){0x001FFFFF, 0, 0, 16 }, + Package(){0x001FFFFF, 1, 0, 17 }, + Package(){0x001FFFFF, 2, 0, 18 }, + Package(){0x001FFFFF, 3, 0, 19 }, + /* D30: SerialIo and SCS */ + Package(){0x001EFFFF, 0, 0, 20 }, + Package(){0x001EFFFF, 1, 0, 21 }, + Package(){0x001EFFFF, 2, 0, 22 }, + Package(){0x001EFFFF, 3, 0, 23 }, + /* D29: PCI Express Port 9-16 */ + Package(){0x001DFFFF, 0, 0, 16 }, + Package(){0x001DFFFF, 1, 0, 17 }, + Package(){0x001DFFFF, 2, 0, 18 }, + Package(){0x001DFFFF, 3, 0, 19 }, + /* D28: PCI Express Port 1-8 */ + Package(){0x001CFFFF, 0, 0, 16 }, + Package(){0x001CFFFF, 1, 0, 17 }, + Package(){0x001CFFFF, 2, 0, 18 }, + Package(){0x001CFFFF, 3, 0, 19 }, + /* D27: PCI Express Port 17-20 */ + Package(){0x001BFFFF, 0, 0, 16 }, + Package(){0x001BFFFF, 1, 0, 17 }, + Package(){0x001BFFFF, 2, 0, 18 }, + Package(){0x001BFFFF, 3, 0, 19 }, + /* D25: SerialIo */ + Package(){0x0019FFFF, 0, 0, 32 }, + Package(){0x0019FFFF, 1, 0, 33 }, + Package(){0x0019FFFF, 2, 0, 34 }, + /* D22: CSME (HECI, IDE-R, Keyboard and Text redirection */ + Package(){0x0016FFFF, 0, 0, 16 }, + Package(){0x0016FFFF, 1, 0, 17 }, + Package(){0x0016FFFF, 2, 0, 18 }, + Package(){0x0016FFFF, 3, 0, 19 }, + /* D21: SerialIo */ + Package(){0x0015FFFF, 0, 0, 16 }, + Package(){0x0015FFFF, 1, 0, 17 }, + Package(){0x0015FFFF, 2, 0, 18 }, + Package(){0x0015FFFF, 3, 0, 19 }, + /* D20: xHCI, OTG, + * Thermal Subsystem, Camera IO Host Controller + */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + /* D19: Integrated Sensor Hub */ + Package(){0x0013FFFF, 0, 0, 20 }, + + /* Host Bridge */ + /* P.E.G. Root Port D1F0 */ + Package(){0x0001FFFF, 0, 0, 16 }, + Package(){0x0001FFFF, 1, 0, 17 }, + Package(){0x0001FFFF, 2, 0, 18 }, + Package(){0x0001FFFF, 3, 0, 19 }, + /* P.E.G. Root Port D1F1 */ + /* P.E.G. Root Port D1F2 */ + /* SA IGFX Device */ + Package(){0x0002FFFF, 0, 0, 16 }, + /* SA Thermal Device */ + Package(){0x0004FFFF, 0, 0, 16 }, + /* SA SkyCam Device */ + Package(){0x0005FFFF, 0, 0, 16 }, + /* SA GMM Device */ + Package(){0x0008FFFF, 0, 0, 16 }, }) } Else { Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // Audio DSP (Smart Sound) 0:13.0 - Package() { 0x0013ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + /* D31 */ + Package() { 0x001fffff, 0, \_SB.PCI0.LNKA, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LNKB, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LNKC, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LNKD, 0 }, + /* D29 */ + Package() { 0x001dffff, 0, \_SB.PCI0.LNKA, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LNKB, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LNKD, 0 }, + /* D28 */ + Package() { 0x001cffff, 0, \_SB.PCI0.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LNKD, 0 }, + /* D27 */ + Package() { 0x001bffff, 0, \_SB.PCI0.LNKA, 0 }, + Package() { 0x001bffff, 1, \_SB.PCI0.LNKB, 0 }, + Package() { 0x001bffff, 2, \_SB.PCI0.LNKC, 0 }, + Package() { 0x001bffff, 3, \_SB.PCI0.LNKD, 0 }, + /* D23 */ + Package() { 0x0017ffff, 0, \_SB.PCI0.LNKA, 0 }, + /* D22 */ + Package() { 0x0016ffff, 0, \_SB.PCI0.LNKA, 0 }, + Package() { 0x0016ffff, 1, \_SB.PCI0.LNKB, 0 }, + Package() { 0x0016ffff, 2, \_SB.PCI0.LNKC, 0 }, + Package() { 0x0016ffff, 3, \_SB.PCI0.LNKD, 0 }, + /* D20 */ + Package() { 0x0014ffff, 0, \_SB.PCI0.LNKA, 0 }, + Package() { 0x0014ffff, 1, \_SB.PCI0.LNKB, 0 }, + Package() { 0x0014ffff, 2, \_SB.PCI0.LNKC, 0 }, + Package() { 0x0014ffff, 3, \_SB.PCI0.LNKD, 0 }, + /* Host bridge */ + Package() { 0x0001ffff, 0, \_SB.PCI0.LNKA, 0 }, + Package() { 0x0001ffff, 1, \_SB.PCI0.LNKB, 0 }, + Package() { 0x0001ffff, 2, \_SB.PCI0.LNKC, 0 }, + Package() { 0x0001ffff, 3, \_SB.PCI0.LNKD, 0 }, + /* SA IGFX Device */ + Package() { 0x0002ffff, 0, \_SB.PCI0.LNKA, 0 }, + /* SA Thermal Device */ + Package() { 0x0004ffff, 0, \_SB.PCI0.LNKA, 0 }, + /* SA Skycam Device */ + Package() { 0x0005ffff, 0, \_SB.PCI0.LNKA, 0 }, + /* SA GMM Device */ + Package() { 0x0008ffff, 0, \_SB.PCI0.LNKA, 0 }, }) } } diff --git a/src/soc/intel/skylake/acpi/pcie.asl b/src/soc/intel/skylake/acpi/pcie.asl index a48bdde0e3..7ab78e0b09 100644 --- a/src/soc/intel/skylake/acpi/pcie.asl +++ b/src/soc/intel/skylake/acpi/pcie.asl @@ -3,6 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,7 +16,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ /* Intel PCH PCIe support */ @@ -29,10 +30,10 @@ Method (IRQM, 1, Serialized) { Package() { 0x0000ffff, 2, 0, 18 }, Package() { 0x0000ffff, 3, 0, 19 } }) Name (IQAP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } }) + Package() { 0x0000ffff, 0, \_SB.PCI0.LNKA, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LNKD, 0 } }) /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ Name (IQBA, Package() { @@ -41,10 +42,10 @@ Method (IRQM, 1, Serialized) { Package() { 0x0000ffff, 2, 0, 19 }, Package() { 0x0000ffff, 3, 0, 16 } }) Name (IQBP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } }) + Package() { 0x0000ffff, 0, \_SB.PCI0.LNKB, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LNKC, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LNKD, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LNKA, 0 } }) /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ Name (IQCA, Package() { @@ -53,10 +54,10 @@ Method (IRQM, 1, Serialized) { Package() { 0x0000ffff, 2, 0, 16 }, Package() { 0x0000ffff, 3, 0, 17 } }) Name (IQCP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } }) + Package() { 0x0000ffff, 0, \_SB.PCI0.LNKC, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LNKD, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LNKA, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LNKB, 0 } }) /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ Name (IQDA, Package() { @@ -65,10 +66,10 @@ Method (IRQM, 1, Serialized) { Package() { 0x0000ffff, 2, 0, 17 }, Package() { 0x0000ffff, 3, 0, 18 } }) Name (IQDP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } }) + Package() { 0x0000ffff, 0, \_SB.PCI0.LNKD, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LNKA, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LNKB, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LNKC, 0 } }) Switch (ToInteger (Arg0)) { /* PCIe Root Port 1 and 5 */ @@ -121,11 +122,9 @@ Device (RP01) { Name (_ADR, 0x001c0000) - #include "pcie_port.asl" - Method (_PRT) { - Return (IRQM (RPPN)) + Return (IRQM (RPA1)) } } @@ -133,11 +132,9 @@ Device (RP02) { Name (_ADR, 0x001c0001) - #include "pcie_port.asl" - Method (_PRT) { - Return (IRQM (RPPN)) + Return (IRQM (RPA2)) } } @@ -145,11 +142,9 @@ Device (RP03) { Name (_ADR, 0x001c0002) - #include "pcie_port.asl" - Method (_PRT) { - Return (IRQM (RPPN)) + Return (IRQM (RPA3)) } } @@ -157,11 +152,9 @@ Device (RP04) { Name (_ADR, 0x001c0003) - #include "pcie_port.asl" - Method (_PRT) { - Return (IRQM (RPPN)) + Return (IRQM (RPA4)) } } @@ -169,11 +162,9 @@ Device (RP05) { Name (_ADR, 0x001c0004) - #include "pcie_port.asl" - Method (_PRT) { - Return (IRQM (RPPN)) + Return (IRQM (RPA5)) } } @@ -181,11 +172,9 @@ Device (RP06) { Name (_ADR, 0x001c0005) - #include "pcie_port.asl" - Method (_PRT) { - Return (IRQM (RPPN)) + Return (IRQM (RPA6)) } } @@ -193,11 +182,9 @@ Device (RP07) { Name (_ADR, 0x001c0006) - #include "pcie_port.asl" - Method (_PRT) { - Return (IRQM (RPPN)) + Return (IRQM (RPA7)) } } @@ -205,10 +192,48 @@ Device (RP08) { Name (_ADR, 0x001c0007) - #include "pcie_port.asl" - Method (_PRT) { - Return (IRQM (RPPN)) + Return (IRQM (RPA8)) } } +Device (RP09) +{ + Name (_ADR, 0x001D0000) + + Method (_PRT) + { + Return (IRQM (RPA9)) + } +} + +Device (RP10) +{ + Name (_ADR, 0x001D0001) + + Method (_PRT) + { + Return (IRQM (RPAA)) + } +} + +Device (RP11) +{ + Name (_ADR, 0x001D0002) + + Method (_PRT) + { + Return (IRQM (RPAB)) + } +} + +Device (RP12) +{ + Name (_ADR, 0x001D0003) + + Method (_PRT) + { + Return (IRQM (RPAC)) + } +} + diff --git a/src/soc/intel/skylake/acpi/pcie_port.asl b/src/soc/intel/skylake/acpi/pcie_port.asl deleted file mode 100644 index 32267461b7..0000000000 --- a/src/soc/intel/skylake/acpi/pcie_port.asl +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Included in each PCIe Root Port device */ - -OperationRegion (RPCS, PCI_Config, 0x00, 0xFF) -Field (RPCS, AnyAcc, NoLock, Preserve) -{ - Offset (0x4c), // Link Capabilities - , 24, - RPPN, 8, // Root Port Number -} diff --git a/src/soc/intel/skylake/acpi/platform.asl b/src/soc/intel/skylake/acpi/platform.asl index f63168a745..2bbe97be80 100644 --- a/src/soc/intel/skylake/acpi/platform.asl +++ b/src/soc/intel/skylake/acpi/platform.asl @@ -3,6 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,7 +16,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ /* The APM port can be used for generating software SMIs */ @@ -43,7 +44,8 @@ Method (TRAP, 1, Serialized) Return (SMIF) // Return value of SMI handler } -/* The _PIC method is called by the OS to choose between interrupt +/* + * The _PIC method is called by the OS to choose between interrupt * routing via the i8259 interrupt controller or the APIC. * * _PIC is called with a parameter of 0 for i8259 configuration and diff --git a/src/soc/intel/skylake/acpi/sata.asl b/src/soc/intel/skylake/acpi/sata.asl deleted file mode 100644 index 0af2a3f3f5..0000000000 --- a/src/soc/intel/skylake/acpi/sata.asl +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -// Intel SATA Controller 0:1f.2 -Device (SATA) -{ - Name (_ADR, 0x001f0002) -} diff --git a/src/soc/intel/skylake/acpi/serialio.asl b/src/soc/intel/skylake/acpi/serialio.asl index 7ffc671a74..203dbef7c5 100644 --- a/src/soc/intel/skylake/acpi/serialio.asl +++ b/src/soc/intel/skylake/acpi/serialio.asl @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,20 +15,22 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ +#include <soc/irq.h> // Intel Serial IO Devices in ACPI Mode -// Serial IO Device BAR0 and BAR1 is 4KB +/* Serial IO Device BAR0 and BAR1 is 4KB */ #define SIO_BAR_LEN 0x1000 -// Put SerialIO device in D0 state -// Arg0 - BAR1 of device -// Arg1 - Set if device is in ACPI mode +/* Put SerialIO device in D0 state */ +/* Arg0 - BAR1 of device */ +/* Arg1 - Set if device is in ACPI mode */ + Method (LPD0, 2, Serialized) { - // PCI mode devices will be handled by OS PCI bus driver + /* PCI mode devices will be handled by OS PCI bus driver */ If (LEqual (Arg1, 0)) { Return } @@ -39,146 +42,80 @@ Method (LPD0, 2, Serialized) } And (SPCS, 0xFFFFFFFC, SPCS) - Store (SPCS, Local0) // Read back after writing + /* Read back after writing */ + Store (SPCS, Local0) } -// Put SerialIO device in D3 state -// Arg0 - BAR1 of device -// Arg1 - Set if device is in ACPI mode +/* Put SerialIO device in D3 state */ +/* Arg0 - BAR1 of device */ +/* Arg1 - Set if device is in ACPI mode */ + Method (LPD3, 2, Serialized) { - // PCI mode devices will be handled by OS PCI bus driver + /* PCI mode devices will be handled by OS PCI bus driver */ If (LEqual (Arg1, 0)) { Return } - OperationRegion (SPRT, SystemMemory, Add (Arg0, 0x84), 4) Field (SPRT, DWordAcc, NoLock, Preserve) { SPCS, 32 } - Or (SPCS, 0x3, SPCS) Store (SPCS, Local0) // Read back after writing } -// Serial IO Resource Consumption for BAR1 +/* Serial IO Resource Consumption for BAR1 */ Device (SIOR) { Name (_HID, EISAID("PNP0C02")) - Name (_UID, 4) - - Name (RBUF, ResourceTemplate() - { - // Serial IO BAR1 (PCI config space) resources - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D0) // SDMA - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D1) // I2C0 - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D2) // I2C1 - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D3) // SPI0 - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D4) // SPI1 - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D5) // UART0 - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D6) // UART1 - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D7) // SDIO - }) - - // Update BAR1 address and length if set in NVS - Method (_CRS, 0, NotSerialized) + Name (_UID, 5) + Method(ADDB,3,Serialized) { + Name (BUFF, ResourceTemplate() { - // SDMA - If (LNotEqual (\S0B1, Zero)) { - CreateDwordField (^RBUF, ^B1D0._BAS, B0AD) - CreateDwordField (^RBUF, ^B1D0._LEN, B0LN) - Store (\S0B1, B0AD) - Store (SIO_BAR_LEN, B0LN) - } - - // I2C0 - If (LNotEqual (\S1B1, Zero)) { - CreateDwordField (^RBUF, ^B1D1._BAS, B1AD) - CreateDwordField (^RBUF, ^B1D1._LEN, B1LN) - Store (\S1B1, B1AD) - Store (SIO_BAR_LEN, B1LN) - } - - // I2C1 - If (LNotEqual (\S2B1, Zero)) { - CreateDwordField (^RBUF, ^B1D2._BAS, B2AD) - CreateDwordField (^RBUF, ^B1D2._LEN, B2LN) - Store (\S2B1, B2AD) - Store (SIO_BAR_LEN, B2LN) - } - - // SPI0 - If (LNotEqual (\S3B1, Zero)) { - CreateDwordField (^RBUF, ^B1D3._BAS, B3AD) - CreateDwordField (^RBUF, ^B1D3._LEN, B3LN) - Store (\S3B1, B3AD) - Store (SIO_BAR_LEN, B3LN) - } - - // SPI1 - If (LNotEqual (\S4B1, Zero)) { - CreateDwordField (^RBUF, ^B1D4._BAS, B4AD) - CreateDwordField (^RBUF, ^B1D4._LEN, B4LN) - Store (\S4B1, B4AD) - Store (SIO_BAR_LEN, B4LN) - } - - // UART0 - If (LNotEqual (\S5B1, Zero)) { - CreateDwordField (^RBUF, ^B1D5._BAS, B5AD) - CreateDwordField (^RBUF, ^B1D5._LEN, B5LN) - Store (\S5B1, B5AD) - Store (SIO_BAR_LEN, B5LN) - } - - // UART1 - If (LNotEqual (\S6B1, Zero)) { - CreateDwordField (^RBUF, ^B1D6._BAS, B6AD) - CreateDwordField (^RBUF, ^B1D6._LEN, B6LN) - Store (\S6B1, B6AD) - Store (SIO_BAR_LEN, B6LN) - } - - // SDIO - If (LNotEqual (\S7B1, Zero)) { - CreateDwordField (^RBUF, ^B1D7._BAS, B7AD) - CreateDwordField (^RBUF, ^B1D7._LEN, B7LN) - Store (\S7B1, B7AD) - Store (SIO_BAR_LEN, B7LN) - } - - Return (RBUF) + Memory32Fixed (ReadWrite, 0x00000000, 0x1000, BUF) + }) + CreateDWordField(BUFF,BUF._BAS,ADDR) + CreateDWordField(BUFF,BUF._LEN,LENG) + Store(ResourceTemplate(){}, Local0) + //Return (RBUF) } } -Device (SDMA) +Device (I2C0) { - // Serial IO DMA Controller - Name (_HID, "INTL9C60") + /* Serial IO I2C0 Controller */ + Name (_HID,"INT3442") Name (_UID, 1) Name (_ADR, 0x00150000) + Name (SSCN, Package () { 432, 507, 30 }) + Name (FMCN, Package () { 72, 160, 30 }) - // BAR0 is assigned during PCI enumeration and saved into NVS + /* BAR0 is assigned during PCI enumeration and saved into NVS */ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { LPSS_I2C0_IRQ } }) + /* DMA channels are only used if Serial IO DMA controller is enabled */ + Name (DBUF, ResourceTemplate () + { + FixedDMA (0x18, 4, Width32Bit, DMA1) // Tx + FixedDMA (0x19, 5, Width32Bit, DMA2) // Rx + }) Method (_CRS, 0, NotSerialized) { - // Update BAR0 address and length if set in NVS + /* Update BAR0 address and length if set in NVS */ If (LNotEqual (\S0B0, Zero)) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) Store (\S0B0, B0AD) Store (SIO_BAR_LEN, B0LN) } - Return (RBUF) } - Method (_STA, 0, NotSerialized) { If (LEqual (\S0EN, 0)) { @@ -187,59 +124,56 @@ Device (SDMA) Return (0xF) } } -} -Device (I2C0) -{ - // Serial IO I2C0 Controller - Method (_HID) + Method (_PS0, 0, Serialized) { - If (\ISWP ()) { - // WildcatPoint - Return ("INT3432") - } + ^^LPD0 (\S0B1, \S0EN) + } - // LynxPoint-LP - Return ("INT33C2") + Method (_PS3, 0, Serialized) + { + ^^LPD3 (\S0B1, \S0EN) } + +} + +Device (I2C1) +{ + /* Serial IO I2C1 Controller */ + Name (_HID,"INT3443") Name (_UID, 1) Name (_ADR, 0x00150001) + Name (SSCN, Package () { 528, 640, 30 }) + Name (FMCN, Package () { 128, 160, 30 }) + Name (FPCN, Package () { 48, 64, 30}) - Name (SSCN, Package () { 432, 507, 30 }) - Name (FMCN, Package () { 72, 160, 30 }) - - // BAR0 is assigned during PCI enumeration and saved into NVS + /* BAR0 is assigned during PCI enumeration and saved into NVS */ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { LPSS_I2C1_IRQ } }) - // DMA channels are only used if Serial IO DMA controller is enabled + /* DMA channels are only used if + * Serial IO DMA controller is enabled + */ Name (DBUF, ResourceTemplate () { - FixedDMA (0x18, 4, Width32Bit, DMA1) // Tx - FixedDMA (0x19, 5, Width32Bit, DMA2) // Rx + FixedDMA (0x1A, 6, Width32Bit, DMA1) // Tx + FixedDMA (0x1B, 7, Width32Bit, DMA2) // Rx }) - Method (_CRS, 0, NotSerialized) { - // Update BAR0 address and length if set in NVS + /* Update BAR0 address and length if set in NVS */ If (LNotEqual (\S1B0, Zero)) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) Store (\S1B0, B0AD) Store (SIO_BAR_LEN, B0LN) } - - // Check if Serial IO DMA Controller is enabled - If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { - Return (ConcatenateResTemplate (RBUF, DBUF)) - } Else { - Return (RBUF) - } + Return (RBUF) } - Method (_STA, 0, NotSerialized) { If (LEqual (\S1EN, 0)) { @@ -260,42 +194,36 @@ Device (I2C0) } } -Device (I2C1) -{ - // Serial IO I2C1 Controller - Method (_HID) - { - If (\ISWP ()) { - // WildcatPoint - Return ("INT3433") - } - // LynxPoint-LP - Return ("INT33C3") - } +Device (I2C2) +{ + /* Serial IO I2C1 Controller */ + Name (_HID,"INT3444") Name (_UID, 1) Name (_ADR, 0x00150002) - Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) - // BAR0 is assigned during PCI enumeration and saved into NVS + /* BAR0 is assigned during PCI enumeration and saved into NVS */ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { LPSS_I2C2_IRQ } }) - // DMA channels are only used if Serial IO DMA controller is enabled + /* DMA channels are only used if + * Serial IO DMA controller is enabled + */ Name (DBUF, ResourceTemplate () { - FixedDMA (0x1A, 6, Width32Bit, DMA1) // Tx - FixedDMA (0x1B, 7, Width32Bit, DMA2) // Rx + FixedDMA (0x1A, 6, Width32Bit, DMA1) + FixedDMA (0x1B, 7, Width32Bit, DMA2) }) Method (_CRS, 0, NotSerialized) { - // Update BAR0 address and length if set in NVS + /* Update BAR0 address and length if set in NVS */ If (LNotEqual (\S2B0, Zero)) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) @@ -303,12 +231,8 @@ Device (I2C1) Store (SIO_BAR_LEN, B0LN) } - // Check if Serial IO DMA Controller is enabled - If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { - Return (ConcatenateResTemplate (RBUF, DBUF)) - } Else { - Return (RBUF) - } + /* Check if Serial IO DMA Controller is enabled */ + Return (RBUF) } Method (_STA, 0, NotSerialized) @@ -331,32 +255,35 @@ Device (I2C1) } } -Device (SPI0) +Device (I2C3) { - // Serial IO SPI0 Controller - Method (_HID) - { - If (\ISWP ()) { - // WildcatPoint - Return ("INT3430") - } - - // LynxPoint-LP - Return ("INT33C0") - } + /* Serial IO I2C3 Controller */ + Name (_HID,"INT3445") Name (_UID, 1) Name (_ADR, 0x00150003) + Name (SSCN, Package () { 432, 507, 30 }) + Name (FMCN, Package () { 72, 160, 30 }) - // BAR0 is assigned during PCI enumeration and saved into NVS + /* BAR0 is assigned during PCI enumeration and saved into NVS */ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { LPSS_I2C3_IRQ } + }) + + /* DMA channels are only used if + * Serial IO DMA controller is enabled + */ + Name (DBUF, ResourceTemplate () + { + FixedDMA (0x1A, 6, Width32Bit, DMA1) + FixedDMA (0x1B, 7, Width32Bit, DMA2) }) Method (_CRS, 0, NotSerialized) { - // Update BAR0 address and length if set in NVS + /* Update BAR0 address and length if set in NVS */ If (LNotEqual (\S3B0, Zero)) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) @@ -364,6 +291,7 @@ Device (SPI0) Store (SIO_BAR_LEN, B0LN) } + /* Check if Serial IO DMA Controller is enabled */ Return (RBUF) } @@ -385,56 +313,48 @@ Device (SPI0) { ^^LPD3 (\S3B1, \S3EN) } + } -Device (SPI1) +Device (I2C4) { - // Serial IO SPI1 Controller - Method (_HID) - { - If (\ISWP ()) { - // WildcatPoint - Return ("INT3431") - } - - // LynxPoint-LP - Return ("INT33C1") - } + /* Serial IO I2C4 Controller */ + Name (_HID,"INT3446") Name (_UID, 1) - Name (_ADR, 0x00150004) + Name (_ADR, 0x00190002) + Name (SSCN, Package () { 432, 507, 30 }) + Name (FMCN, Package () { 72, 160, 30 }) - // BAR0 is assigned during PCI enumeration and saved into NVS + /* BAR0 is assigned during PCI enumeration and saved into NVS */ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { LPSS_I2C4_IRQ } }) - // DMA channels are only used if Serial IO DMA controller is enabled + /* DMA channels are only used if + * Serial IO DMA controller is enabled + */ Name (DBUF, ResourceTemplate () { - FixedDMA (0x10, 0, Width32Bit, DMA1) // Tx - FixedDMA (0x11, 1, Width32Bit, DMA2) // Rx + FixedDMA (0x1A, 6, Width32Bit, DMA1) + FixedDMA (0x1B, 7, Width32Bit, DMA2) }) Method (_CRS, 0, NotSerialized) { - // Update BAR0 address and length if set in NVS - If (LNotEqual (\S4B0, Zero)) { + /* Update BAR0 address and length if set in NVS*/ + If (LNotEqual (\S4B0, Zero)) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) Store (\S4B0, B0AD) Store (SIO_BAR_LEN, B0LN) } - // Check if Serial IO DMA Controller is enabled - If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { - Return (ConcatenateResTemplate (RBUF, DBUF)) - } Else { - Return (RBUF) - } + /* Check if Serial IO DMA Controller is enabled */ + Return (RBUF) } - Method (_STA, 0, NotSerialized) { If (LEqual (\S4EN, 0)) { @@ -455,52 +375,43 @@ Device (SPI1) } } -Device (UAR0) +Device (I2C5) { - // Serial IO UART0 Controller - Method (_HID) - { - If (\ISWP ()) { - // WildcatPoint - Return ("INT3434") - } - - // LynxPoint-LP - Return ("INT33C4") - } + /* Serial IO I2C1 Controller */ + Name (_HID,"INT3447") Name (_UID, 1) - Name (_ADR, 0x00150005) + Name (_ADR, 0x00190002) + Name (SSCN, Package () { 432, 507, 30 }) + Name (FMCN, Package () { 72, 160, 30 }) - // BAR0 is assigned during PCI enumeration and saved into NVS + /* BAR0 is assigned during PCI enumeration and saved into NVS */ Name (RBUF, ResourceTemplate () { - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13} + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { LPSS_I2C5_IRQ } }) - // DMA channels are only used if Serial IO DMA controller is enabled + /* DMA channels are only used if + * Serial IO DMA controller is enabled + */ Name (DBUF, ResourceTemplate () { - FixedDMA (0x16, 2, Width32Bit, DMA1) // Tx - FixedDMA (0x17, 3, Width32Bit, DMA2) // Rx + FixedDMA (0x1A, 6, Width32Bit, DMA1) + FixedDMA (0x1B, 7, Width32Bit, DMA2) }) Method (_CRS, 0, NotSerialized) { - // Update BAR0 address and length if set in NVS - If (LNotEqual (\S5B0, Zero)) { - CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) - CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S5B0, B0AD) - Store (SIO_BAR_LEN, B0LN) - } + /* Update BAR0 address and length if set in NVS */ + CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) + CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) + Store (0xFE02A000, B0AD) + Store (SIO_BAR_LEN, B0LN) - // Check if Serial IO DMA Controller is enabled - If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { - Return (ConcatenateResTemplate (RBUF, DBUF)) - } Else { - Return (RBUF) - } + + /* Check if Serial IO DMA Controller is enabled */ + Return (RBUF) } Method (_STA, 0, NotSerialized) @@ -523,32 +434,24 @@ Device (UAR0) } } -Device (UAR1) +Device (SPI0) { - // Serial IO UART1 Controller - Method (_HID) - { - If (\ISWP ()) { - // WildcatPoint - Return ("INT3435") - } - - // LynxPoint-LP - Return ("INT33C5") - } + /* Serial IO PI0 Controller */ + Name (_HID,"INT3440") Name (_UID, 1) - Name (_ADR, 0x00150006) + Name (_ADR, 0x001E0002) - // BAR0 is assigned during PCI enumeration and saved into NVS + /* BAR0 is assigned during PCI enumeration and saved into NVS */ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { LPSS_SPI0_IRQ } }) Method (_CRS, 0, NotSerialized) { - // Update BAR0 address and length if set in NVS + /* Update BAR0 address and length if set in NVS */ If (LNotEqual (\S6B0, Zero)) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) @@ -567,7 +470,6 @@ Device (UAR1) Return (0xF) } } - Method (_PS0, 0, Serialized) { ^^LPD0 (\S6B1, \S6EN) @@ -579,37 +481,129 @@ Device (UAR1) } } -Device (SDIO) +Device (SPI1) { - // Serial IO SDIO Controller - Method (_HID) + /* Serial IO SPI1 Controller */ + Name (_HID,"INT3441") + Name (_UID, 1) + Name (_ADR, 0x001E0003) + + /* BAR0 is assigned during PCI enumeration and saved into NVS */ + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { LPSS_SPI1_IRQ } + }) + + /* DMA channels are only used if Serial IO DMA controller is enabled */ + Name (DBUF, ResourceTemplate () + { + FixedDMA (0x10, 0, Width32Bit, DMA1) /* Tx */ + FixedDMA (0x11, 1, Width32Bit, DMA2) /* Rx */ + }) + Method (_CRS, 0, NotSerialized) { - If (\ISWP ()) { - // WildcatPoint - Return ("INT3436") + /* Update BAR0 address and length if set in NVS */ + If (LNotEqual (\S7B0, Zero)) { + CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) + CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) + Store (\S7B0, B0AD) + Store (SIO_BAR_LEN, B0LN) } - // LynxPoint-LP - Return ("INT33C6") + Return (RBUF) + } + Method (_STA, 0, NotSerialized) + { + If (LEqual (\S7EN, 0)) { + Return (0x0) + } Else { + Return (0xF) + } + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (\S7B1, \S7EN) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (\S7B1, \S7EN) + } +} + +Device (UAR0) +{ + /* Serial IO UART0 Controller */ + Name (_HID,"INT3448") + Name (_UID, 1) + Name (_ADR, 0x001E0000) + + /* BAR0 is assigned during PCI enumeration and saved into NVS */ + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { LPSS_UART0_IRQ } + }) + + Method (_CRS, 0, NotSerialized) + { + /* Update BAR0 address and length if set in NVS */ + If (LNotEqual (\S8B0, Zero)) { + CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) + CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) + Store (\S8B0, B0AD) + Store (SIO_BAR_LEN, B0LN) + } + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + If (LEqual (\S8EN, 0)) { + Return (0x0) + } Else { + Return (0xF) + } + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (\S8B1, \S8EN) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (\S8B1, \S8EN) } - Name (_CID, "PNP0D40") +} + +Device (UAR1) +{ + /* Serial IO UART1 Controller */ + Name (_HID,"INT3449") Name (_UID, 1) - Name (_ADR, 0x00170000) + Name (_ADR, 0x001E0001) - // BAR0 is assigned during PCI enumeration and saved into NVS + /* BAR0 is assigned during PCI enumeration and saved into NVS */ Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {5} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { LPSS_UART1_IRQ } }) Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S7B0, Zero)) { + If (LNotEqual (\S9B0, Zero)) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S7B0, B0AD) + Store (\S9B0, B0AD) Store (SIO_BAR_LEN, B0LN) } @@ -618,10 +612,97 @@ Device (SDIO) Method (_STA, 0, NotSerialized) { - If (LEqual (\S7EN, 0)) { + If (LEqual (\S9EN, 0)) { Return (0x0) } Else { Return (0xF) } } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (\S9B1, \S9EN) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (\S9B1, \S9EN) + } } + +Device (UAR2) +{ + /* Serial IO UART1 Controller */ + Name (_HID,"INT344A") + Name (_UID, 1) + Name (_ADR, 0x00190000) + + /* BAR0 is assigned during PCI enumeration and saved into NVS */ + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { LPSS_UART2_IRQ } + }) + + Method (_CRS, 0, NotSerialized) + { + /* Update BAR0 address and length if set in NVS */ + If (LNotEqual (\SAB0, Zero)) { + CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) + CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) + Store (\SAB0, B0AD) + Store (SIO_BAR_LEN, B0LN) + } + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + If (LEqual (\SAEN, 0)) { + Return (0x0) + } Else { + Return (0xF) + } + } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (\SAB1, \SAEN) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (\SAB1, \SAEN) + } +} + + +Device (PEMC) +{ + Name (_ADR, 0x001E0004) + Device (CARD) + { + Name (_ADR, 0x00000008) + Method (_RMV, 0x0, NotSerialized) + { + Return (0) + } + } +} + +/* SD controller */ +Device (PSDC) +{ + Name (_ADR, 0x001E0006) + Device (CARD) + { + Name (_ADR, 0x00000008) + Method (_RMV, 0x0, NotSerialized) + { + Return (1) + } + } +} + diff --git a/src/soc/intel/skylake/acpi/sleepstates.asl b/src/soc/intel/skylake/acpi/sleepstates.asl index 6fea862d86..dda7d14029 100644 --- a/src/soc/intel/skylake/acpi/sleepstates.asl +++ b/src/soc/intel/skylake/acpi/sleepstates.asl @@ -3,6 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,7 +16,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ Name (\_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) diff --git a/src/soc/intel/skylake/acpi/smbus.asl b/src/soc/intel/skylake/acpi/smbus.asl index 15bcfde69a..31a5114792 100644 --- a/src/soc/intel/skylake/acpi/smbus.asl +++ b/src/soc/intel/skylake/acpi/smbus.asl @@ -3,6 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,14 +16,14 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ // Intel SMBus Controller 0:1f.3 Device (SBUS) { - Name (_ADR, 0x001f0003) + Name (_ADR, 0x001f0004) #ifdef ENABLE_SMBUS_METHODS OperationRegion (SMBP, PCI_Config, 0x00, 0x100) diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl index c2049ea2e3..b8fec94e9e 100644 --- a/src/soc/intel/skylake/acpi/systemagent.asl +++ b/src/soc/intel/skylake/acpi/systemagent.asl @@ -3,6 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,11 +16,14 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <soc/iomap.h> +#define BASE_32GB 0x800000000 +#define SIZE_16GB 0x400000000 + Name (_HID, EISAID ("PNP0A08")) // PCIe Name (_CID, EISAID ("PNP0A03")) // PCI @@ -33,12 +37,86 @@ Device (MCHC) OperationRegion (MCHP, PCI_Config, 0x00, 0x100) Field (MCHP, DWordAcc, NoLock, Preserve) { + Offset(0x40), // EPBAR (0:0:0:40) + EPEN, 1, // Enable + , 11, + EPBR, 20, // EPBAR [31:12] + + Offset(0x48), // MCHBAR (0:0:0:48) + MHEN, 1, // Enable + , 14, + MHBR, 17, // MCHBAR [31:15] + + Offset(0x54), // DEVEN (0:0:0:54) + D0EN, 1, // DEV0 Enable + D1F2, 1, // DEV1 FUN2 Enable + D1F1, 1, // DEV1 FUN1 Enable + D1F0, 1, // DEV1 FUN0 Enable + + Offset(0x60), // PCIEXBAR (0:0:0:60) + PXEN, 1, // Enable + PXSZ, 2, // PCI Express Size + , 23, + PXBR, 6, // PCI Express BAR [31:26] + + Offset(0x68), // DMIBAR (0:0:0:68) + DIEN, 1, // Enable + , 11, + DIBR, 20, // DMIBAR [31:12] + Offset (0x70), // ME Base Address - MEBA, 64, + MEBA, 64, + + Offset(0x80), // PAM0 Register (0:0:0:80) + PMLK, 1, // PAM Lock bit. + , 3, + PM0H, 2, // PAM 0, High Nibble + , 2, + + Offset(0x81), // PAM1 Register (0:0:0:81) + PM1L, 2, // PAM1, Low Nibble + , 2, + PM1H, 2, // PAM1, High Nibble + , 2, + + Offset(0x82), // PAM2 Register (0:0:0:82) + PM2L, 2, // PAM2, Low Nibble + , 2, + PM2H, 2, // PAM2, High Nibble + , 2, + + Offset(0x83), // PAM3 Register (0:0:0:83) + PM3L, 2, // PAM3, Low Nibble + , 2, + PM3H, 2, // PAM3, High Nibble + , 2, + + Offset(0x84), // PAM4 Register (0:0:0:84) + PM4L, 2, // PAM4, Low Nibble + , 2, + PM4H, 2, // PAM4, High Nibble + , 2, + + Offset(0x85), // PAM5 Register (0:0:0:85) + PM5L, 2, // PAM5, Low Nibble + , 2, + PM5H, 2, // PAM5, High Nibble + , 2, + + Offset(0x86), // PAM6 Register (0:0:0:86) + PM6L, 2, // PAM6, Low Nibble + , 2, + PM6H, 2, // PAM6, High Nibble + , 2, + Offset (0xa0), // Top of Used Memory - TOM, 64, + TOM, 64, + + Offset (0xa8), // Top of Upper Used Memory + TUUD, 64, + Offset (0xbc), // Top of Low Used Memory - TLUD, 32, + TLUD, 32, } } @@ -48,161 +126,311 @@ Method (_CRS, 0, Serialized) { Name (MCRS, ResourceTemplate() { - // Bus Numbers + /* Bus Numbers */ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - // IO Region 0 + /* IO Region 0 */ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - // PCI Config Space + /* PCI Config Space */ Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - // IO Region 1 + /* IO Region 1 */ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - // VGA memory (0xa0000-0xbffff) + /* VGA memory (0xa0000-0xbffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, 0x00020000,,, ASEG) - // OPROM reserved (0xc0000-0xc3fff) + /* OPROM reserved (0xc0000-0xc3fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, 0x00004000,,, OPR0) - // OPROM reserved (0xc4000-0xc7fff) + /* OPROM reserved (0xc4000-0xc7fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, 0x00004000,,, OPR1) - // OPROM reserved (0xc8000-0xcbfff) + /* OPROM reserved (0xc8000-0xcbfff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, 0x00004000,,, OPR2) - // OPROM reserved (0xcc000-0xcffff) + /* OPROM reserved (0xcc000-0xcffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, 0x00004000,,, OPR3) - // OPROM reserved (0xd0000-0xd3fff) + /* OPROM reserved (0xd0000-0xd3fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, 0x00004000,,, OPR4) - // OPROM reserved (0xd4000-0xd7fff) + /* OPROM reserved (0xd4000-0xd7fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, 0x00004000,,, OPR5) - // OPROM reserved (0xd8000-0xdbfff) + /* OPROM reserved (0xd8000-0xdbfff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, 0x00004000,,, OPR6) - // OPROM reserved (0xdc000-0xdffff) + /* OPROM reserved (0xdc000-0xdffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, 0x00004000,,, OPR7) - // BIOS Extension (0xe0000-0xe3fff) + /* BIOS Extension (0xe0000-0xe3fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, 0x00004000,,, ESG0) - // BIOS Extension (0xe4000-0xe7fff) + /* BIOS Extension (0xe4000-0xe7fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, 0x00004000,,, ESG1) - // BIOS Extension (0xe8000-0xebfff) + /* BIOS Extension (0xe8000-0xebfff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, 0x00004000,,, ESG2) - // BIOS Extension (0xec000-0xeffff) + /* BIOS Extension (0xec000-0xeffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000ec000, 0x000effff, 0x00000000, 0x00004000,,, ESG3) - // System BIOS (0xf0000-0xfffff) + /* System BIOS (0xf0000-0xfffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, 0x00010000,,, FSEG) - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) + /* PCI Memory Region (TOLUD - 0xdfffffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, + 0xE0000000,,, PM01) + + /* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x10000, 0x1ffff, 0x00000000, + 0x10000,,, PM02) + + /* PCH reserved resource (0xfd000000-0xfe7fffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, PM01) + 0x00000000, 0xfd000000, 0xfe7fffff, 0x00000000, + 0x1800000,,, PM03) - // TPM Area (0xfed40000-0xfed44fff) + /* TPM Area (0xfed40000-0xfed44fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, 0x00005000,,, TPMR) }) - // Find PCI resource area in MCRS - CreateDwordField(MCRS, PM01._MIN, PMIN) - CreateDwordField(MCRS, PM01._MAX, PMAX) - CreateDwordField(MCRS, PM01._LEN, PLEN) + /* Find PCI resource area in MCRS */ + CreateDwordField (MCRS, PM01._MIN, PMIN) + CreateDwordField (MCRS, PM01._MAX, PMAX) + CreateDwordField (MCRS, PM01._LEN, PLEN) - // Fix up PCI memory region - // Start with Top of Lower Usable DRAM + /* + * Fix up PCI memory region + * Start with Top of Lower Usable DRAM + */ Store (^MCHC.TLUD, Local0) Store (^MCHC.MEBA, Local1) - // Check if ME base is equal + /* Check if ME base is equal */ If (LEqual (Local0, Local1)) { - // Use Top Of Memory instead + /* Use Top Of Memory instead */ Store (^MCHC.TOM, Local0) } Store (Local0, PMIN) - Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) - Add(Subtract(PMAX, PMIN), 1, PLEN) + Add (Subtract (PMAX, PMIN), 1, PLEN) + + /* Patch PM02 range based on Memory Size */ + CreateQwordField (MCRS, PM02._MIN, MMIN) + CreateQwordField (MCRS, PM02._MAX, MMAX) + CreateQwordField (MCRS, PM02._LEN, MLEN) + + Store (^MCHC.TUUD, Local0) + + If (LLessEqual (Local0, BASE_32GB)) + { + Store (BASE_32GB, MMIN) + Store (SIZE_16GB, MLEN) + } + else + { + Store (0, MMIN) + Store (0, MLEN) + } + Subtract (Add (MMIN, MLEN), 1, MMAX) Return (MCRS) } +Name (EP_B, 0) /* to store EP BAR */ +Name (MH_B, 0) /* to store MCH BAR */ +Name (PC_B, 0) /* to store PCIe BAR */ +Name (PC_L, 0) /* to store PCIe BAR Length */ +Name (DM_B, 0) /* to store DMI BAR */ + +/* Get MCH BAR */ +Method (GMHB,0,Serialized) +{ + if (LEqual (MH_B,0)) + { + ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, MH_B) + } + Return (MH_B) +} + +/* Get EP BAR */ +Method (GEPB,0,Serialized) +{ + if (LEqual (EP_B,0)) + { + ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, EP_B) + } + Return (EP_B) +} + +/* Get PCIe BAR */ +Method (GPCB,0,Serialized) +{ + if (LEqual (PC_B,0)) + { + ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, PC_B) + } + Return (PC_B) +} + +/* Get PCIe Length */ +Method (GPCL,0,Serialized) +{ + if (LEqual (PC_L,0)) + { + ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, PC_L) + } + Return (PC_L) +} + +/* Get DMI BAR */ +Method (GDMB,0,Serialized) +{ + if (LEqual (DM_B,0)) + { + ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, DM_B) + } + Return (DM_B) +} + /* PCI Device Resource Consumption */ Device (PDRC) { Name (_HID, EISAID("PNP0C02")) Name (_UID, 1) - Name (PDRS, ResourceTemplate() { - Memory32Fixed (ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) - Memory32Fixed (ReadWrite, MCH_BASE_ADDRESS, MCH_BASE_SIZE) - Memory32Fixed (ReadWrite, DMI_BASE_ADDRESS, DMI_BASE_SIZE) - Memory32Fixed (ReadWrite, EP_BASE_ADDRESS, EP_BASE_SIZE) - Memory32Fixed (ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE) - Memory32Fixed (ReadWrite, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE) - Memory32Fixed (ReadWrite, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE) + Name (BUF0,ResourceTemplate() + { + /* MCH BAR _BAS will be updated in _CRS below according to + * B0:D0:F0:Reg.48h + */ + Memory32Fixed (ReadWrite, 0, 0x08000, MCHB) + + /* DMI BAR _BAS will be updated in _CRS below according to + * B0:D0:F0:Reg.68h + */ + Memory32Fixed (ReadWrite, 0, 0x01000, DMIB) + + /* EP BAR _BAS will be updated in _CRS below according to + * B0:D0:F0:Reg.40h + */ + Memory32Fixed (ReadWrite, 0, 0x01000, EGPB) + + /* PCI Express BAR _BAS and _LEN will be updated in + * _CRS below according to B0:D0:F0:Reg.60h + */ + Memory32Fixed (ReadWrite, 0, 0, PCIX) + + /* MISC ICH TTT base address reserved for the + * TxT module use. + */ + Memory32Fixed (ReadWrite, 0xFED20000, 0x20000) + + /* VTD engine memory range. + * Check if the hard code meets the real configuration. + */ + Memory32Fixed (ReadOnly, 0xFED90000, 0x00004000) + + /* MISC ICH. Check if the hard code meets the + * real configuration. + */ + Memory32Fixed (ReadWrite, 0xFED45000, 0x4B000, TPMM) + + /* FLASH range */ + Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000, FIOH) /* 16MB */ + + /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ + Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH) + + /* Reserve HPET address decode range */ + Memory32Fixed (ReadWrite, 0, 0, HPET) + + /* Debug Base Address + * Base Address for ACPI debug output memory buffer + */ + Memory32Fixed (ReadWrite, 0, 0, DBAD) }) // Current Resource Settings Method (_CRS, 0, Serialized) { - Return (PDRS) + CreateDwordField (BUF0, ^MCHB._BAS, MBR0) + Store (\_SB.PCI0.GMHB(), MBR0) + + CreateDwordField (BUF0, ^DMIB._BAS, DBR0) + Store (\_SB.PCI0.GDMB(), DBR0) + + CreateDwordField (BUF0, ^EGPB._BAS, EBR0) + Store (\_SB.PCI0.GEPB(), EBR0) + + CreateDwordField (BUF0, ^PCIX._BAS, XBR0) + Store (\_SB.PCI0.GPCB(), XBR0) + + CreateDwordField (BUF0, ^PCIX._LEN, XSZ0) + Store (\_SB.PCI0.GPCL(), XSZ0) + + CreateDwordField (BUF0, ^HPET._BAS, HBAS) + CreateDwordField (BUF0, ^HPET._LEN, HLEN) + Store (0xfed00000, HBAS) + Store (0x400, HLEN) + + Return (BUF0) } } diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index c41275ccd2..f0ee414b52 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -3,6 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,17 +16,17 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ -// XHCI Controller 0:14.0 +/* XHCI Controller 0:14.0 */ Device (XHCI) { Name (_ADR, 0x00140000) - Name (PLSD, 5) // Port Link State - RxDetect - Name (PLSP, 7) // Port Link State - Polling + Name (PLSD, 5) /* Port Link State - RxDetect */ + Name (PLSP, 7) /* Port Link State - Polling */ OperationRegion (XPRT, PCI_Config, 0x00, 0x100) Field (XPRT, AnyAcc, NoLock, Preserve) @@ -34,68 +35,74 @@ Device (XHCI) DVID, 16, Offset (0x10), , 16, - XMEM, 16, // MEM_BASE - Offset (0x40), - , 11, - SWAI, 1, - , 20, - Offset (0x44), - , 12, - SAIP, 2, - , 18, + XMEM, 16, /* MEM_BASE */ Offset (0x74), D0D3, 2, , 6, - PMEE, 1, // PME_EN + PMEE, 1, /* PME_EN */ , 6, - PMES, 1, // PME_STS + PMES, 1, /* PME_STS */ + Offset (0xA8), + , 13, + MW13, 1, + MW14, 1, + , 17, Offset (0xb0), , 13, MB13, 1, MB14, 1, + , 17, Offset (0xd0), - PR2R, 32, // USB2PR - PR2M, 32, // USB2PRM - PR3R, 32, // USB3PR - PR3M, 32, // USB3PRM + PR2, 32, /* USB2PR */ + PR2M, 32, /* USB2PRM */ + PR3, 32, /* USB3PR */ + PR3M, 32, /* USB3PRM */ + } + + Method (USRA,0){ + Return(11) } - // Clear status bits + Method (SSPA,0){ + Return (13) + } + + /* Clear status bits */ Method (LPCL, 0, Serialized) { OperationRegion (XREG, SystemMemory, - ShiftLeft (^XMEM, 16), 0x600) + ShiftLeft (^XMEM, 16), 0x600) Field (XREG, DWordAcc, Lock, Preserve) { - Offset (0x510), // PORTSCNUSB3[0] + Offset (0x510), /* PORTSCNUSB3[0]*/ PSC0, 32, - Offset (0x520), // PORTSCNUSB3[1] + Offset (0x520), /* PORTSCNUSB3[1]*/ PSC1, 32, - Offset (0x530), // PORTSCNUSB3[2] + Offset (0x530), /* PORTSCNUSB3[2]*/ PSC2, 32, - Offset (0x540), // PORTSCNUSB3[3] + Offset (0x540), /* PORTSCNUSB3[3]*/ PSC3, 32, } - // Port Enabled/Disabled (Bit 1) + /* Port Enabled/Disabled (Bit 1)*/ Name (PEDB, ShiftLeft (1, 1)) - // Change Status (Bits 23:17) + /* Change Status (Bits 23:17)*/ Name (CHST, ShiftLeft (0x7f, 17)) - // Port 0 + /* Port 0 */ And (PSC0, Not (PEDB), Local0) Or (Local0, CHST, PSC0) - // Port 1 + /* Port 1 */ And (PSC1, Not (PEDB), Local0) Or (Local0, CHST, PSC1) - // Port 2 + /* Port 2 */ And (PSC2, Not (PEDB), Local0) Or (Local0, CHST, PSC2) - // Port 3 + /* Port 3 */ And (PSC3, Not (PEDB), Local0) Or (Local0, CHST, PSC3) } @@ -148,7 +155,7 @@ Device (XHCI) WPR4, 1, // [31] Warm Port Reset } - // Wait for all powered ports to finish polling + /* Wait for all powered ports to finish polling*/ Store (10, Local0) While (LOr (LOr (LAnd (LEqual (PPR1, 1), LEqual (PLS1, PLSP)), LAnd (LEqual (PPR2, 1), LEqual (PLS2, PLSP))), @@ -162,13 +169,13 @@ Device (XHCI) Stall (10) } - // For each USB3 Port: - // If port is disconnected (PLS=5 PP=1 CSC=0) - // 1) Issue warm reset (WPR=1) - // 2) Poll for warm reset complete (WRC=0) - // 3) Write 1 to port status to clear + /* For each USB3 Port:*/ + /* If port is disconnected (PLS=5 PP=1 CSC=0)*/ + /* 1) Issue warm reset (WPR=1)*/ + /* 2) Poll for warm reset complete (WRC=0)*/ + /* 3) Write 1 to port status to clear*/ - // Local# indicate if port is reset + /* Local# indicate if port is reset*/ Store (0, Local1) Store (0, Local2) Store (0, Local3) @@ -176,26 +183,26 @@ Device (XHCI) If (LAnd (LEqual (PLS1, PLSD), LAnd (LEqual (CSC1, 0), LEqual (PPR1, 1)))) { - Store (1, WPR1) // Issue warm reset + Store (1, WPR1) /* Issue warm reset*/ Store (1, Local1) } If (LAnd (LEqual (PLS2, PLSD), LAnd (LEqual (CSC2, 0), LEqual (PPR2, 1)))) { - Store (1, WPR2) // Issue warm reset + Store (1, WPR2) /* Issue warm reset*/ Store (1, Local2) } If (LAnd (LEqual (PLS3, PLSD), LAnd (LEqual (CSC3, 0), LEqual (PPR3, 1)))) { - Store (1, WPR3) // Issue warm reset + Store (1, WPR3) /* Issue warm reset*/ Store (1, Local3) } If (LAnd (LEqual (PLS4, PLSD), LAnd (LEqual (CSC4, 0), LEqual (PPR4, 1)))) { - Store (1, WPR4) // Issue warm reset + Store (1, WPR4) /* Issue warm reset*/ Store (1, Local4) } - // Poll for warm reset complete on all ports that were reset + /* Poll for warm reset complete on all ports that were reset*/ Store (10, Local0) While (LOr (LOr (LAnd (LEqual (Local1, 1), LEqual (WRC1, 0)), LAnd (LEqual (Local2, 1), LEqual (WRC2, 0))), @@ -209,7 +216,7 @@ Device (XHCI) Stall (10) } - // Clear status bits in all ports + /* Clear status bits in all ports */ LPCL () } @@ -220,152 +227,95 @@ Device (XHCI) Method (_PS0, 0, Serialized) { - If (LEqual (^DVID, 0xFFFF)) { - Return () - } - If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { - Return () - } - - OperationRegion (XREG, SystemMemory, - Add (ShiftLeft (^XMEM, 16), 0x8000), 0x200) - Field (XREG, DWordAcc, Lock, Preserve) - { - Offset (0x0e0), // AUX Reset Control 1 - , 15, - AX15, 1, - Offset (0x154), // AUX Domain PM Control Register 2 - , 31, - CLK2, 1, - Offset (0x16c), // AUX Clock Control - , 2, - CLK0, 1, - , 11, - CLK1, 1, // USB3 Port Aux/Core Clock Gating Enable - } - - // If device is in D3, set back to D0 - Store (^D0D3, Local0) - if (LEqual (Local0, 3)) { - Store (0, ^D0D3) - } - - if (LNot (\ISWP())) { - // Clear PCI 0xB0[14:13] - Store (0, ^MB13) - Store (0, ^MB14) - - // Clear MMIO 0x816C[14,2] - Store (0, CLK0) - Store (0, CLK1) - - // Set MMIO 0x8154[31] - Store (1, CLK2) - - // Handle per-port reset if needed - LPS0 () - - // Set MMIO 0x80e0[15] - Store (1, AX15) - - // Clear PCI CFG offset 0x40[11] - Store (0, ^SWAI) - - // Clear PCI CFG offset 0x44[13:12] - Store (0, ^SAIP) - } - - Return () } - Method (_PS3, 0, Serialized) { - If (LEqual (^DVID, 0xFFFF)) { - Return () - } - If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { - Return () - } - - OperationRegion (XREG, SystemMemory, - Add (ShiftLeft (^XMEM, 16), 0x8000), 0x200) - Field (XREG, DWordAcc, Lock, Preserve) - { - Offset (0x0e0), // AUX Reset Control 1 - , 15, - AX15, 1, - Offset (0x154), // AUX Domain PM Control Register 2 - , 31, - CLK2, 1, - Offset (0x16c), // AUX Clock Control - , 2, - CLK0, 1, - , 11, - CLK1, 1, // USB3 Port Aux/Core Clock Gating Enable - } - - Store (1, ^PMES) // Clear PME Status - Store (1, ^PMEE) // Enable PME - - // If device is in D3, set back to D0 - Store (^D0D3, Local0) - if (LEqual (Local0, 3)) { - Store (0, ^D0D3) - } - - if (LNot (\ISWP())) { - // Set PCI 0xB0[14:13] - Store (1, ^MB13) - Store (1, ^MB14) - - // Set MMIO 0x816C[14,2] - Store (1, CLK0) - Store (1, CLK1) - - // Clear MMIO 0x8154[31] - Store (0, CLK2) - - // Clear MMIO 0x80e0[15] - Store (0, AX15) - - // Set PCI CFG offset 0x40[11] - Store (1, ^SWAI) - - // Set PCI CFG offset 0x44[13:12] - Store (1, ^SAIP) - } - - // Put device in D3 - Store (3, ^D0D3) - - Return () } Name (_PRW, Package(){ 0x6d, 3 }) - // Leave USB ports on for to allow Wake from USB + /* Leave USB ports on for to allow Wake from USB */ - Method(_S3D,0) // Highest D State in S3 State + Method (_S3D,0) /* Highest D State in S3 State*/ { Return (3) } - Method(_S4D,0) // Highest D State in S4 State + Method (_S4D,0) /* Highest D State in S4 State*/ { Return (3) } - - Device (HUB7) + Device (HS01) { - Name (_ADR, 0x00000000) - - // How many are there? - Device (PRT1) { Name (_ADR, 1) } // USB Port 0 - Device (PRT2) { Name (_ADR, 2) } // USB Port 1 - Device (PRT3) { Name (_ADR, 3) } // USB Port 2 - Device (PRT4) { Name (_ADR, 4) } // USB Port 3 - Device (PRT5) { Name (_ADR, 5) } // USB Port 4 - Device (PRT6) { Name (_ADR, 6) } // USB Port 5 + Name(_ADR, 0x01) + } + Device (HS02) + { + Name(_ADR, 0x02) + } + Device (HS03) + { + Name(_ADR, 0x03) + } + Device (HS04) + { + Name(_ADR, 0x04) + } + Device (HS05) + { + Name(_ADR, 0x05) + } + Device (HS06) + { + Name(_ADR, 0x06) + } + Device (HS07) + { + Name(_ADR, 0x07) + } + Device (HS08) + { + Name(_ADR, 0x08) + } + Device (HS09) + { + Name(_ADR, 0x09) + } + Device (HS10) + { + Name(_ADR, 0x10) + } + Device (USR1) + { + Method(_ADR) { Return (Add(USRA(),0)) } + } + Device (USR2) + { + Method(_ADR) { Return (Add(USRA(),1)) } + } + Device (SS01) + { + Method(_ADR) { Return (Add(SSPA(),0)) } + } + Device (SS02) + { + Method(_ADR) { Return (Add(SSPA(),1)) } + } + Device (SS03) + { + Method(_ADR) { Return (Add(SSPA(),2)) } + } + Device (SS04) + { + Method(_ADR) { Return (Add(SSPA(),3)) } + } + Device (SS05) + { + Method(_ADR) { Return (Add(SSPA(),4)) } + } + Device (SS06) + { + Method(_ADR) { Return (Add(SSPA(),5)) } } } |