diff options
Diffstat (limited to 'src/soc/intel/skylake/acpi/device_nvs.asl')
-rw-r--r-- | src/soc/intel/skylake/acpi/device_nvs.asl | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/src/soc/intel/skylake/acpi/device_nvs.asl b/src/soc/intel/skylake/acpi/device_nvs.asl deleted file mode 100644 index e84d25ae9b..0000000000 --- a/src/soc/intel/skylake/acpi/device_nvs.asl +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* Device Enabled in ACPI Mode */ - -S0EN, 8, // I2C0 Enable -S1EN, 8, // I2C1 Enable -S2EN, 8, // I2C2 Enable -S3EN, 8, // I2C3 Enable -S4EN, 8, // I2C4 Enable -S5EN, 8, // I2C5 Enable -S6EN, 8, // SPI0 Enable -S7EN, 8, // SPI1 Enable -S8EN, 8, // UART0 Enable -S9EN, 8, // UART1 Enable -SAEN, 8, // UART2 Enable - -/* BAR 0 */ -S0B0, 32, // I2C0 BAR0 -S1B0, 32, // I2C1 BAR0 -S2B0, 32, // I2C2 BAR0 -S3B0, 32, // I2C3 BAR0 -S4B0, 32, // I2C4 BAR0 -S5B0, 32, // I2C5 BAR0 -S6B0, 32, // SPI0 BAR0 -S7B0, 32, // SPI1 BAR0 -S8B0, 32, // UART0 BAR0 -S9B0, 32, // UART1 BAR0 -SAB0, 32, // UART2 BAR0 - -/* BAR 1 */ -S0B1, 32, // I2C0 BAR1 -S1B1, 32, // I2C1 BAR1 -S2B1, 32, // I2C2 BAR1 -S3B1, 32, // I2C3 BAR1 -S4B1, 32, // I2C4 BAR1 -S5B1, 32, // I2C5 BAR1 -S6B1, 32, // SPI0 BAR1 -S7B1, 32, // SPI1 BAR1 -S8B1, 32, // UART0 BAR1 -S9B1, 32, // UART1 BAR1 -SAB1, 32, // UART2 BAR1 - |