diff options
Diffstat (limited to 'src/soc/intel/quark')
| -rw-r--r-- | src/soc/intel/quark/chip.h | 12 | ||||
| -rw-r--r-- | src/soc/intel/quark/include/soc/pci_devs.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/quark/romstage/romstage.c | 54 |
3 files changed, 70 insertions, 1 deletions
diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h index 59c8793dfe..fc9890fde5 100644 --- a/src/soc/intel/quark/chip.h +++ b/src/soc/intel/quark/chip.h @@ -19,11 +19,21 @@ #define _SOC_CHIP_H_ #include <stdint.h> +#include <fsp/util.h> #include <soc/pci_devs.h> #include <soc/pm.h> struct soc_intel_quark_config { - uint32_t junk; + /* + * MemoryInit: + * + * The following fields come from FspUpdVpd.h and are defined as PCDs + * for the FSP binary. Data for these fields comes from the board's + * devicetree.cb file which gets processed into static.c and then + * built into the coreboot image. The fields below contain retain + * the FSP PCD field name. + */ + UINT16 PcdSmmTsegSize; }; extern struct chip_operations soc_ops; diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index d776e1e7d7..4f577cef8e 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -18,6 +18,7 @@ #ifndef _QUARK_PCI_DEVS_H_ #define _QUARK_PCI_DEVS_H_ +#include <arch/io.h> #include <device/pci.h> #include <soc/QuarkNcSocId.h> @@ -31,4 +32,8 @@ # define HSUART1_DEV SIO1_DEV # define HSUART1_FUNC 5 +/* Platform Controller Unit */ +# define LPC_DEV_FUNC PCI_DEVFN(PCI_DEVICE_NUMBER_QNC_LPC, \ + PCI_FUNCTION_NUMBER_QNC_LPC) + #endif /* _QUARK_PCI_DEVS_H_ */ diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 731e52975d..a089185bd0 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -13,9 +13,12 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ #include <arch/early_variables.h> #include <console/console.h> +#include <cbfs.h> +#include "../chip.h" #include <device/pci_def.h> #include <fsp/car.h> #include <fsp/util.h> @@ -47,3 +50,54 @@ struct chipset_power_state *fill_power_state(void) printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); return ps; } + +/* Initialize the UPD parameters for MemoryInit */ +void soc_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *upd) +{ + const struct device *dev; + char *pdat_file; + size_t pdat_file_len; + const struct soc_intel_quark_config *config; + + /* Locate the pdat.bin file */ + pdat_file = cbfs_boot_map_with_leak("pdat.bin", CBFS_TYPE_RAW, + &pdat_file_len); + if (!pdat_file) { + printk(BIOS_DEBUG, + "Platform configuration file (pdat.bin) not found."); + pdat_file_len = 0; + } + + /* Locate the configuration data from devicetree.cb */ + dev = dev_find_slot(0, LPC_DEV_FUNC); + if (!dev) { + printk(BIOS_ERR, + "Error! Device (PCI:0:%02x.%01x) not found, " + "soc_memory_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC, + PCI_FUNCTION_NUMBER_QNC_LPC); + return; + } + config = dev->chip_info; + + /* Set the parameters for MemoryInit */ + printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n"); + upd->PcdSmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + config->PcdSmmTsegSize : 0; + upd->PcdPlatformDataBaseAddress = (UINT32)pdat_file; + upd->PcdPlatformDataMaxLen = (UINT32)pdat_file_len; +} + +void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, + MEMORY_INIT_UPD *new) +{ + /* Display the parameters for MemoryInit */ + printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); + fsp_display_upd_value("PcdSmmTsegSize", 2, + old->PcdSmmTsegSize, new->PcdSmmTsegSize); + fsp_display_upd_value("PcdPlatformDataBaseAddress", 4, + old->PcdPlatformDataBaseAddress, + new->PcdPlatformDataBaseAddress); + fsp_display_upd_value("PcdPlatformDataMaxLen", 4, + old->PcdPlatformDataMaxLen, new->PcdPlatformDataMaxLen); +} |