diff options
Diffstat (limited to 'src/soc/intel/quark/romstage')
| -rw-r--r-- | src/soc/intel/quark/romstage/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/quark/romstage/romstage.c | 10 | ||||
| -rw-r--r-- | src/soc/intel/quark/romstage/uart.c | 42 |
3 files changed, 8 insertions, 45 deletions
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 2f29b06a70..6c92ac4474 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -20,4 +20,3 @@ romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c romstage-y += romstage.c -romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index c86c2eae3d..5be022a8d6 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -58,11 +58,17 @@ static const struct reg_script i2c_gpio_controller_init[] = { REG_SCRIPT_END }; +static const struct reg_script hsuart_init[] = { + /* Enable the HSUART */ + REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS), + REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), + REG_SCRIPT_END +}; + void car_soc_pre_console_init(void) { if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) - set_base_address_and_enable_uart(0, HSUART1_DEV, HSUART1_FUNC, - UART_BASE_ADDRESS); + reg_script_run_on_dev(HSUART1_BDF, hsuart_init); } void car_soc_post_console_init(void) diff --git a/src/soc/intel/quark/romstage/uart.c b/src/soc/intel/quark/romstage/uart.c deleted file mode 100644 index 9e8f6c529b..0000000000 --- a/src/soc/intel/quark/romstage/uart.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2006-2010 coresystems GmbH - * Copyright (C) 2015-2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include <device/pci.h> -#include <device/pci_def.h> -#include <rules.h> -#include <soc/romstage.h> - -int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base) -{ - uint16_t reg16; - - /* HSUART controller #1 (B0:D20:F5). */ - pci_devfn_t uart_bdf = PCI_DEV(bus, dev, func); - - /* Decode BAR0(offset 0x10). */ - pci_write_config32(uart_bdf, PCI_BASE_ADDRESS_0, mmio_base); - - /* Enable MEMBASE at CMD(offset 0x04). */ - reg16 = pci_read_config16(uart_bdf, PCI_COMMAND); - reg16 |= PCI_COMMAND_MEMORY; - pci_write_config16(uart_bdf, PCI_COMMAND, reg16); - - return 0; -} |