diff options
Diffstat (limited to 'src/soc/intel/pantherlake/include')
| -rw-r--r-- | src/soc/intel/pantherlake/include/soc/bootblock.h | 13 | ||||
| -rw-r--r-- | src/soc/intel/pantherlake/include/soc/iomap.h | 94 | ||||
| -rw-r--r-- | src/soc/intel/pantherlake/include/soc/p2sb.h | 14 | ||||
| -rw-r--r-- | src/soc/intel/pantherlake/include/soc/pci_devs.h | 240 | ||||
| -rw-r--r-- | src/soc/intel/pantherlake/include/soc/pcr_ids.h | 28 | ||||
| -rw-r--r-- | src/soc/intel/pantherlake/include/soc/pm.h | 161 | ||||
| -rw-r--r-- | src/soc/intel/pantherlake/include/soc/smbus.h | 8 | ||||
| -rw-r--r-- | src/soc/intel/pantherlake/include/soc/soc_info.h | 16 |
8 files changed, 574 insertions, 0 deletions
diff --git a/src/soc/intel/pantherlake/include/soc/bootblock.h b/src/soc/intel/pantherlake/include/soc/bootblock.h new file mode 100644 index 0000000000..165edf70de --- /dev/null +++ b/src/soc/intel/pantherlake/include/soc/bootblock.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PANTHERLAKE_BOOTBLOCK_H_ +#define _SOC_PANTHERLAKE_BOOTBLOCK_H_ + +/* Bootblock pre console init programming */ +void bootblock_pcd_die_early_init(void); + +/* Bootblock post console init programming */ +void bootblock_pcd_die_init(void); +void report_platform_info(void); + +#endif diff --git a/src/soc/intel/pantherlake/include/soc/iomap.h b/src/soc/intel/pantherlake/include/soc/iomap.h new file mode 100644 index 0000000000..dbabfd6796 --- /dev/null +++ b/src/soc/intel/pantherlake/include/soc/iomap.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PANTHERLAKE_IOMAP_H_ +#define _SOC_PANTHERLAKE_IOMAP_H_ + +#include <soc/pcr_ids.h> + +/* + * Memory-mapped I/O registers. + */ + +#define PCH_PRESERVED_BASE_ADDRESS 0xfd800000 +#define PCH_PRESERVED_BASE_SIZE 0x1000000 + +#define MCH_BASE_ADDRESS 0xfedc0000 +#define MCH_BASE_SIZE 0x20000 + +/* System Agent Fabric (SAF) */ +/* TODO: Update with latest value */ +#define SAF_BASE_ADDRESS 0x3ffe000000 +#define SAF_BASE_SIZE 0x2000000 + +#define EP_BASE_ADDRESS 0xfeda1000 +#define EP_BASE_SIZE 0x1000 + +#define HPET_BASE_ADDRESS 0xfed00000 + +#define PCH_PWRM_BASE_ADDRESS 0xfe000000 +#define PCH_PWRM_BASE_SIZE 0x10000 + +#define GPIO_BASE_SIZE 0x10000 + +#define HECI1_BASE_ADDRESS 0xfeda2000 + +/* VT-d 512KB */ +#define VTD_BASE_ADDRESS 0xfc800000 +#define VTD_BASE_SIZE 0x80000 + +/* GFX VT-d 64KB */ +#define GFXVT_BASE_ADDRESS 0xfc800000 +#define GFXVT_BASE_SIZE 0x10000 + +/* Non-GFX VT-d 64KB */ +#define VTVC0_BASE_ADDRESS 0xfc810000 +#define VTVC0_BASE_SIZE 0x10000 + +/* IOC VT-d 64KB */ +#define IOCVTD_BASE_ADDRESS 0xfc820000 +#define IOCVTD_BASE_SIZE 0x10000 + +#define UART_BASE_SIZE 0x1000 +#define UART_BASE_0_ADDRESS CONFIG_CONSOLE_UART_BASE_ADDRESS +/* Both UART BAR 0 and 1 are 4KB in size */ +#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ + UART_BASE_SIZE * (x))) +#define UART_BASE(x) UART_BASE_0_ADDR(x) + +#define EARLY_GSPI_BASE_ADDRESS 0xfe030000 + +#define EARLY_I2C_BASE_ADDRESS 0xfe020000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) + +#define SPI_BASE_ADDRESS 0xfe010000 + +/* REGBAR 128MB */ +#define REG_BASE_ADDRESS 0xf0000000 +#define REG_BASE_SIZE (128 * MiB) + +#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS +#define P2SB_SIZE (256 * MiB) + +/* PCH P2SB2 256MB */ +#define P2SB2_BAR CONFIG_P2SB_2_PCR_BASE_ADDRESS +#define P2SB2_SIZE (256 * MiB) +#define IOE_P2SB_BAR P2SB2_BAR +#define IOE_P2SB_SIZE P2SB2_SIZE + +/* IOM_BASE_ADDR = ((long int) Ps2bMmioBase | (int) (((Offset) & 0x0F0000) << 8) \ + * | ((unsigned char)(Pid) << 16) | (short int) ((Offset) & 0xFFFF)) + * + * Where, Ps2bMmioBase = 0x4010000000, Offset = 0x0, Pid = 0x80 + */ +#define IOM_BASE_ADDR 0x4010800000 +#define IOM_BASE_SIZE 0x10000 +#define IOM_BASE_ADDR_MAX ((IOM_BASE_ADDR + IOM_BASE_SIZE) - 1) + +/* I/O port address space */ +#define ACPI_BASE_ADDRESS 0x1800 +#define ACPI_BASE_SIZE 0x100 + +#define TCO_BASE_ADDRESS 0x400 +#define TCO_BASE_SIZE 0x20 + +#endif /* _SOC_PANTHERLAKE_IOMAP_H_ */ diff --git a/src/soc/intel/pantherlake/include/soc/p2sb.h b/src/soc/intel/pantherlake/include/soc/p2sb.h new file mode 100644 index 0000000000..c431ad6d12 --- /dev/null +++ b/src/soc/intel/pantherlake/include/soc/p2sb.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PANTHERLAKE_P2SB_H_ +#define _SOC_PANTHERLAKE_P2SB_H_ + +#define HPTC_OFFSET 0x60 +#define HPTC_ADDR_ENABLE_BIT BIT(7) + +#define PCH_P2SB_EPMASK0 0x220 + +extern struct device_operations soc_p2sb_ops; +extern struct device_operations soc_p2sb_2_ops; + +#endif /* _SOC_PANTHERLAKE_P2SB_H_ */ diff --git a/src/soc/intel/pantherlake/include/soc/pci_devs.h b/src/soc/intel/pantherlake/include/soc/pci_devs.h new file mode 100644 index 0000000000..dc419d022f --- /dev/null +++ b/src/soc/intel/pantherlake/include/soc/pci_devs.h @@ -0,0 +1,240 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PANTHERLAKE_PCI_DEVS_H_ +#define _SOC_PANTHERLAKE_PCI_DEVS_H_ + +#include <device/pci_def.h> + +#define _PCI_DEVFN(slot, func) PCI_DEVFN(PCI_DEV_SLOT_ ## slot, func) +#if !defined(__SIMPLE_DEVICE__) +#include <device/device.h> +#define _PCI_DEV(slot, func) pcidev_path_on_root_debug(_PCI_DEVFN(slot, func), __func__) +#else +#define _PCI_DEV(slot, func) PCI_DEV(0, PCI_DEV_SLOT_ ## slot, func) +#endif + +/* System Agent Devices */ +#define PCI_DEV_SLOT_ROOT 0x00 +#define PCI_DEVFN_ROOT _PCI_DEVFN(ROOT, 0) +#if defined(__SIMPLE_DEVICE__) +#define PCI_DEV_ROOT _PCI_DEV(ROOT, 0) +#endif + +#define PCI_DEV_SLOT_IGD 0x02 +#define PCI_DEVFN_IGD _PCI_DEVFN(IGD, 0) +#define PCI_DEV_IGD _PCI_DEV(IGD, 0) + +#define PCI_DEV_SLOT_DPTF 0x04 +#define PCI_DEVFN_DPTF _PCI_DEVFN(DPTF, 0) +#define PCI_DEV_DPTF _PCI_DEV(DPTF, 0) + +#define PCI_DEV_SLOT_IPU 0x05 +#define PCI_DEVFN_IPU _PCI_DEVFN(IPU, 0) +#define PCI_DEV_IPU _PCI_DEV(IPU, 0) + +#define PCI_DEV_SLOT_PCIE_2 0x06 +#define PCI_DEVFN_PCIE9 _PCI_DEVFN(PCIE_2, 0) +#define PCI_DEVFN_PCIE10 _PCI_DEVFN(PCIE_2, 1) +#define PCI_DEVFN_PCIE11 _PCI_DEVFN(PCIE_2, 2) +#define PCI_DEVFN_PCIE12 _PCI_DEVFN(PCIE_2, 3) +#define PCI_DEV_PCIE9 _PCI_DEV(PCIE_2, 0) +#define PCI_DEV_PCIE10 _PCI_DEV(PCIE_2, 1) +#define PCI_DEV_PCIE11 _PCI_DEV(PCIE_2, 2) +#define PCI_DEV_PCIE12 _PCI_DEV(PCIE_2, 3) + +#define PCI_DEV_SLOT_TBT 0x07 +#define PCI_DEVFN_TBT(x) _PCI_DEVFN(TBT, (x)) +#define NUM_TBT_FUNCTIONS 4 +#define PCI_DEVFN_TBT0 _PCI_DEVFN(TBT, 0) +#define PCI_DEVFN_TBT1 _PCI_DEVFN(TBT, 1) +#define PCI_DEVFN_TBT2 _PCI_DEVFN(TBT, 2) +#define PCI_DEVFN_TBT3 _PCI_DEVFN(TBT, 3) +#define PCI_DEV_TBT0 _PCI_DEV(TBT, 0) +#define PCI_DEV_TBT1 _PCI_DEV(TBT, 1) +#define PCI_DEV_TBT2 _PCI_DEV(TBT, 2) +#define PCI_DEV_TBT3 _PCI_DEV(TBT, 3) + +#define PCI_DEV_SLOT_TELEMETRY 0x0a +#define PCI_DEVFN_TELEMETRY _PCI_DEVFN(TELEMETRY, 0) +#define PCI_DEV_TELEMETRY _PCI_DEV(TELEMETRY, 0) + +#define PCI_DEV_SLOT_NPU 0x0b +#define PCI_DEVFN_NPU _PCI_DEVFN(NPU, 0) +#define PCI_DEV_NPU _PCI_DEV(NPU, 0) + +#define PCI_DEV_SLOT_IAA 0x0c +#define PCI_DEVFN_IAA _PCI_DEVFN(IAA, 0) +#define PCI_DEV_IAA _PCI_DEV(IAA, 0) + + +#define PCI_DEV_SLOT_TCSS 0x0d +#define NUM_TCSS_DMA_FUNCTIONS 2 +#define PCI_DEVFN_TCSS_DMA(x) _PCI_DEVFN(TCSS, ((x) + 2)) +#define PCI_DEVFN_TCSS_XHCI _PCI_DEVFN(TCSS, 0) +#define PCI_DEVFN_TCSS_XDCI _PCI_DEVFN(TCSS, 1) +#define PCI_DEVFN_TCSS_DMA0 _PCI_DEVFN(TCSS, 2) +#define PCI_DEVFN_TCSS_DMA1 _PCI_DEVFN(TCSS, 3) +#define PCI_DEV_TCSS_XHCI _PCI_DEV(TCSS, 0) +#define PCI_DEV_TCSS_XDCI _PCI_DEV(TCSS, 1) +#define PCI_DEV_TCSS_DMA0 _PCI_DEV(TCSS, 2) +#define PCI_DEV_TCSS_DMA1 _PCI_DEV(TCSS, 3) + +#define PCI_DEV_SLOT_THC 0x10 +#define PCI_DEVFN_THC0 _PCI_DEVFN(THC, 0) +#define PCI_DEVFN_THC1 _PCI_DEVFN(THC, 1) +#define PCI_DEV_THC0 _PCI_DEV(THC, 0) +#define PCI_DEV_THC1 _PCI_DEV(THC, 1) + +#define PCI_DEV_SLOT_I3C 0x11 +#define PCI_DEVFN_I3C1 _PCI_DEVFN(I3C, 0) +#define PCI_DEVFN_I3C2 _PCI_DEVFN(I3C, 2) +#define PCI_DEV_I3C1 _PCI_DEV(I3C, 0) +#define PCI_DEV_I3C2 _PCI_DEV(I3C, 2) + +#define PCI_DEV_SLOT_ISH 0x12 +#define PCI_DEVFN_ISH _PCI_DEVFN(ISH, 0) +#define PCI_DEVFN_P2SB2 _PCI_DEVFN(ISH, 1) +#define PCI_DEVFN_IEH_1 _PCI_DEVFN(ISH, 3) +#define PCI_DEVFN_GSPI2 _PCI_DEVFN(ISH, 6) +#define PCI_DEV_ISH _PCI_DEV(ISH, 0) +#define PCI_DEV_P2SB2 _PCI_DEV(ISH, 1) +#define PCI_DEV_IEH_1 _PCI_DEV(ISH, 3) +#define PCI_DEV_GSPI2 _PCI_DEV(ISH, 6) + +#define PCI_DEV_SLOT_XHCI 0x14 +#define PCI_DEVFN_XHCI _PCI_DEVFN(XHCI, 0) +#define PCI_DEVFN_USBOTG _PCI_DEVFN(XHCI, 1) +#define PCI_DEVFN_SRAM _PCI_DEVFN(XHCI, 2) +#define PCI_DEVFN_CNVI_WIFI _PCI_DEVFN(XHCI, 3) +#define PCI_DEVFN_IEH_0 _PCI_DEVFN(XHCI, 5) +#define PCI_DEVFN_CNVI_BT _PCI_DEVFN(XHCI, 7) +#define PCI_DEV_XHCI _PCI_DEV(XHCI, 0) +#define PCI_DEV_USBOTG _PCI_DEV(XHCI, 1) +#define PCI_DEV_SRAM _PCI_DEV(XHCI, 2) +#define PCI_DEV_CNVI_WIFI _PCI_DEV(XHCI, 3) +#define PCI_DEV_IEH_0 _PCI_DEV(XHCI, 5) +#define PCI_DEV_CNVI_BT _PCI_DEV(XHCI, 7) + +#define PCI_DEV_SLOT_SIO0 0x15 +#define PCI_DEVFN_I2C0 _PCI_DEVFN(SIO0, 0) +#define PCI_DEVFN_I2C1 _PCI_DEVFN(SIO0, 1) +#define PCI_DEVFN_I2C2 _PCI_DEVFN(SIO0, 2) +#define PCI_DEVFN_I2C3 _PCI_DEVFN(SIO0, 3) +#define PCI_DEV_I2C0 _PCI_DEV(SIO0, 0) +#define PCI_DEV_I2C1 _PCI_DEV(SIO0, 1) +#define PCI_DEV_I2C2 _PCI_DEV(SIO0, 2) +#define PCI_DEV_I2C3 _PCI_DEV(SIO0, 3) + +#define PCI_DEV_SLOT_CSE 0x16 +#define PCI_DEVFN_CSE _PCI_DEVFN(CSE, 0) +#define PCI_DEVFN_CSE_2 _PCI_DEVFN(CSE, 1) +#define PCI_DEVFN_CSE_IDER _PCI_DEVFN(CSE, 2) +#define PCI_DEVFN_CSE_KT _PCI_DEVFN(CSE, 3) +#define PCI_DEVFN_CSE_3 _PCI_DEVFN(CSE, 4) +#define PCI_DEVFN_CSE_4 _PCI_DEVFN(CSE, 5) +#define PCI_DEV_CSE _PCI_DEV(CSE, 0) +#define PCI_DEV_CSE_2 _PCI_DEV(CSE, 1) +#define PCI_DEV_CSE_IDER _PCI_DEV(CSE, 2) +#define PCI_DEV_CSE_KT _PCI_DEV(CSE, 3) +#define PCI_DEV_CSE_3 _PCI_DEV(CSE, 4) +#define PCI_DEV_CSE_4 _PCI_DEV(CSE, 5) + +#define PCI_DEV_SLOT_ESE 0x18 +#define PCI_DEVFN_ESE1 _PCI_DEVFN(ESE, 0) +#define PCI_DEVFN_ESE2 _PCI_DEVFN(ESE, 1) +#define PCI_DEVFN_ESE3 _PCI_DEVFN(ESE, 2) +#define PCI_DEV_ESE1 _PCI_DEV(ESE, 0) +#define PCI_DEV_ESE2 _PCI_DEV(ESE, 1) +#define PCI_DEV_ESE3 _PCI_DEV(ESE, 2) + +#define PCI_DEV_SLOT_SIO1 0x19 +#define PCI_DEVFN_I2C4 _PCI_DEVFN(SIO1, 0) +#define PCI_DEVFN_I2C5 _PCI_DEVFN(SIO1, 1) +#define PCI_DEVFN_UART2 _PCI_DEVFN(SIO1, 2) +#define PCI_DEV_I2C4 _PCI_DEV(SIO1, 0) +#define PCI_DEV_I2C5 _PCI_DEV(SIO1, 1) +#define PCI_DEV_UART2 _PCI_DEV(SIO1, 2) + +#define PCI_DEV_SLOT_PCIE_1 0x1c +#define PCI_DEVFN_PCIE1 _PCI_DEVFN(PCIE_1, 0) +#define PCI_DEVFN_PCIE2 _PCI_DEVFN(PCIE_1, 1) +#define PCI_DEVFN_PCIE3 _PCI_DEVFN(PCIE_1, 2) +#define PCI_DEVFN_PCIE4 _PCI_DEVFN(PCIE_1, 3) +#define PCI_DEVFN_PCIE5 _PCI_DEVFN(PCIE_1, 4) +#define PCI_DEVFN_PCIE6 _PCI_DEVFN(PCIE_1, 5) +#define PCI_DEVFN_PCIE7 _PCI_DEVFN(PCIE_1, 6) +#define PCI_DEVFN_PCIE8 _PCI_DEVFN(PCIE_1, 7) + +#define PCI_DEV_PCIE1 _PCI_DEV(PCIE_1, 0) +#define PCI_DEV_PCIE2 _PCI_DEV(PCIE_1, 1) +#define PCI_DEV_PCIE3 _PCI_DEV(PCIE_1, 2) +#define PCI_DEV_PCIE4 _PCI_DEV(PCIE_1, 3) +#define PCI_DEV_PCIE5 _PCI_DEV(PCIE_1, 4) +#define PCI_DEV_PCIE6 _PCI_DEV(PCIE_1, 5) +#define PCI_DEV_PCIE7 _PCI_DEV(PCIE_1, 6) +#define PCI_DEV_PCIE8 _PCI_DEV(PCIE_1, 7) + +#define PCI_DEV_SLOT_SIO2 0x1e +#define PCI_DEVFN_UART0 _PCI_DEVFN(SIO2, 0) +#define PCI_DEVFN_UART1 _PCI_DEVFN(SIO2, 1) +#define PCI_DEVFN_GSPI0 _PCI_DEVFN(SIO2, 2) +#define PCI_DEVFN_GSPI1 _PCI_DEVFN(SIO2, 3) +#define PCI_DEVFN_TSN1 _PCI_DEVFN(SIO2, 4) +#define PCI_DEVFN_TSN2 _PCI_DEVFN(SIO2, 5) +#define PCI_DEV_UART0 _PCI_DEV(SIO2, 0) +#define PCI_DEV_UART1 _PCI_DEV(SIO2, 1) +#define PCI_DEV_GSPI0 _PCI_DEV(SIO2, 2) +#define PCI_DEV_GSPI1 _PCI_DEV(SIO2, 3) + +#define PCI_DEV_SLOT_ESPI 0x1f +#define PCI_DEVFN_ESPI _PCI_DEVFN(ESPI, 0) +#define PCI_DEVFN_P2SB _PCI_DEVFN(ESPI, 1) +#define PCI_DEVFN_PMC _PCI_DEVFN(ESPI, 2) +#define PCI_DEVFN_HDA _PCI_DEVFN(ESPI, 3) +#define PCI_DEVFN_SMBUS _PCI_DEVFN(ESPI, 4) +#define PCI_DEVFN_SPI _PCI_DEVFN(ESPI, 5) +#define PCI_DEVFN_GBE _PCI_DEVFN(ESPI, 6) +#define PCI_DEVFN_NPK _PCI_DEVFN(ESPI, 7) +#define PCI_DEV_ESPI _PCI_DEV(ESPI, 0) +#define PCI_DEV_P2SB _PCI_DEV(ESPI, 1) + +#if !ENV_RAMSTAGE +/* + * PCI_DEV_PMC is intentionally not defined in RAMSTAGE since PMC device gets + * hidden from PCI bus after call to FSP-S. This leads to resource allocator + * dropping it from the root bus as unused device. All references to PCI_DEV_PMC + * would then return NULL and can go unnoticed if not handled properly. Since, + * this device does not have any special chip config associated with it, it is + * okay to not provide the definition for it in ramstage. + */ +#define PCI_DEV_PMC _PCI_DEV(ESPI, 2) +#endif + +#define PCI_DEV_HDA _PCI_DEV(ESPI, 3) +#define PCI_DEV_SMBUS _PCI_DEV(ESPI, 4) +#define PCI_DEV_SPI _PCI_DEV(ESPI, 5) +#define PCI_DEV_GBE _PCI_DEV(ESPI, 6) +#define PCI_DEV_NPK _PCI_DEV(ESPI, 7) + +#endif + +/* for common code */ +#define MIN_PCH_SLOT PCI_DEV_SLOT_THC +#define PCH_DEV_SLOT_CSE PCI_DEV_SLOT_CSE +#define PCH_DEVFN_CSE PCI_DEVFN_CSE +#define PCH_DEV_CSE PCI_DEV_CSE +#define PCH_DEV_SPI PCI_DEV_SPI +#define PCH_DEV_LPC PCI_DEV_ESPI +#define PCH_DEV_P2SB PCI_DEV_P2SB +#define PCI_DEV_IOE_P2SB PCI_DEV_P2SB2 +#define PCH_DEV_SMBUS PCI_DEV_SMBUS +#define PCH_DEV_XHCI PCI_DEV_XHCI +#define PCH_DEVFN_XHCI PCI_DEVFN_XHCI +#define PCH_DEVFN_PMC PCI_DEVFN_PMC +#define PCH_DEV_SLOT_ISH PCI_DEV_SLOT_ISH +#define SA_DEV_ROOT PCI_DEV_ROOT +#define SA_DEVFN_ROOT PCI_DEVFN_ROOT +#define SA_DEVFN_TCSS_DMA0 PCI_DEVFN_TCSS_DMA0 +#define SA_DEVFN_TCSS_DMA1 PCI_DEVFN_TCSS_DMA1 +#define SA_DEV_IGD PCI_DEV_IGD +#define SA_DEVFN_IGD PCI_DEVFN_IGD diff --git a/src/soc/intel/pantherlake/include/soc/pcr_ids.h b/src/soc/intel/pantherlake/include/soc/pcr_ids.h new file mode 100644 index 0000000000..8e655540bc --- /dev/null +++ b/src/soc/intel/pantherlake/include/soc/pcr_ids.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PANTHERLAKE_PCR_H_ +#define _SOC_PANTHERLAKE_PCR_H_ + +/* Port IDs */ + +#define PID_XHCI 0x09 +#define PID_DMI 0x2F +#define PID_CSME0 0x40 +#define PID_GPIOCOM0 0x59 +#define PID_GPIOCOM1 0x5A +#define PID_GPIOCOM3 0x5B +#define PID_GPIOCOM4 0x5C +#define PID_GPIOCOM5 0x5D +#define PID_ITSS 0x69 +#define PID_PSTH 0x6A +#define PID_RTC 0x6C +#define PID_ISCLK 0x72 +#define PID_IOM 0x80 +#define PID_PSF4 0xB0 +#define PID_PSF6 0xB1 +#define PID_PSF8 0xB2 +#define PID_PSF14 0xB3 +#define PID_PSF15 0xB4 +#define PID_PSF0 0xB5 + +#endif /* _SOC_PANTHERLAKE_PCR_H_ */ diff --git a/src/soc/intel/pantherlake/include/soc/pm.h b/src/soc/intel/pantherlake/include/soc/pm.h new file mode 100644 index 0000000000..b8a86fc83a --- /dev/null +++ b/src/soc/intel/pantherlake/include/soc/pm.h @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PANTHERLAKE_PM_H_ +#define _SOC_PANTHERLAKE_PM_H_ + +#define PM1_STS 0x00 +#define WAK_STS BIT(15) +#define PCIEXPWAK_STS BIT(14) +#define PRBTNOR_STS BIT(11) +#define RTC_STS BIT(10) +#define PWRBTN_STS BIT(8) +#define GBL_STS BIT(5) +#define BM_STS BIT(4) +#define TMROF_STS BIT(0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS BIT(14) +#define RTC_EN BIT(10) +#define PWRBTN_EN BIT(8) +#define GBL_EN BIT(5) +#define TMROF_EN BIT(0) +#define PM1_CNT 0x04 +#define GBL_RLS BIT(2) +#define BM_RLD BIT(1) +#define SCI_EN BIT(0) +#define PM1_TMR 0x08 +#define SMI_EN 0x30 +#define XHCI_SMI_EN BIT(31) +#define ME_SMI_EN BIT(30) +#define ESPI_SMI_EN BIT(28) +#define GPIO_UNLOCK_SMI_EN BIT(27) +#define INTEL_USB2_EN BIT(18) +#define LEGACY_USB2_EN BIT(17) +#define PERIODIC_EN BIT(14) +#define TCO_SMI_EN BIT(13) +#define MCSMI_EN BIT(11) +#define BIOS_RLS BIT(7) +#define SWSMI_TMR_EN BIT(6) +#define APMC_EN BIT(5) +#define SLP_SMI_EN BIT(4) +#define LEGACY_USB_EN BIT(3) +#define BIOS_EN BIT(2) +#define EOS BIT(1) +#define GBL_SMI_EN BIT(0) +#define SMI_STS 0x34 +#define SMI_STS_BITS 32 +#define XHCI_SMI_STS_BIT 31 +#define ME_SMI_STS_BIT 30 +#define ESPI_SMI_STS_BIT 28 +#define GPIO_UNLOCK_SMI_STS_BIT 27 +#define SPI_SMI_STS_BIT 26 +#define SCC_SMI_STS_BIT 25 +#define MONITOR_STS_BIT 21 +#define PCI_EXP_SMI_STS_BIT 20 +#define SMBUS_SMI_STS_BIT 16 +#define SERIRQ_SMI_STS_BIT 15 +#define PERIODIC_STS_BIT 14 +#define TCO_STS_BIT 13 +#define DEVMON_STS_BIT 12 +#define MCSMI_STS_BIT 11 +#define GPIO_STS_BIT 10 +#define GPE0_STS_BIT 9 +#define PM1_STS_BIT 8 +#define SWSMI_TMR_STS_BIT 6 +#define APM_STS_BIT 5 +#define SMI_ON_SLP_EN_STS_BIT 4 +#define LEGACY_USB_STS_BIT 3 +#define BIOS_STS_BIT 2 +#define GPE_CNTL 0x42 +#define SWGPE_CTRL BIT(1) +#define DEVACT_STS 0x44 +#define PM2_CNT 0x50 + +#define GPE0_REG_MAX 4 +#define GPE0_REG_SIZE 32 +#define GPE0_STS(x) (0x60 + ((x) * 4)) +#define GPE_31_0 0 /* 0x60/0x70 = GPE[31:0] */ +#define GPE_63_32 1 /* 0x64/0x74 = GPE[63:32] */ +#define GPE_95_64 2 /* 0x68/0x78 = GPE[95:64] */ +#define GPE_STD 3 /* 0x6c/0x7c = Standard GPE */ +#define GPE_STS_RSVD GPE_STD +#define WADT_STS BIT(18) +#define GPIO_T2_STS BIT(15) +#define ESPI_STS BIT(14) +#define PME_B0_STS BIT(13) +#define ME_SCI_STS BIT(12) +#define PME_STS BIT(11) +#define BATLOW_STS BIT(10) +#define PCI_EXP_STS BIT(9) +#define SMB_WAK_STS BIT(7) +#define TCOSCI_STS BIT(6) +#define SWGPE_STS BIT(2) +#define HOT_PLUG_STS BIT(1) +#define GPE0_EN(x) (0x70 + ((x) * 4)) +#define WADT_EN BIT(18) +#define GPIO_T2_EN BIT(15) +#define ESPI_EN BIT(14) +#define PME_B0_EN_BIT 13 +#define PME_B0_EN BIT(PME_B0_EN_BIT) +#define ME_SCI_EN BIT(12) +#define PME_EN BIT(11) +#define BATLOW_EN BIT(10) +#define PCI_EXP_EN BIT(9) +#define TCOSCI_EN BIT(6) +#define SWGPE_EN BIT(2) +#define HOT_PLUG_EN BIT(1) + +/* + * Enable SMI generation: + * - on APMC writes (io 0xb2) + * - on writes to SLP_EN (sleep states) + * - on writes to GBL_RLS (bios commands) + * - on eSPI events (does nothing on LPC systems) + * No SMIs: + * - on TCO events, unless enabled in common code + * - on microcontroller writes (io 0x62/0x66) + */ +#define ENABLE_SMI_PARAMS \ + (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) + +#define PSS_RATIO_STEP 2 +#define PSS_MAX_ENTRIES 8 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +#if !defined(__ACPI__) + +#include <acpi/acpi.h> +#include <soc/gpe.h> +#include <soc/iomap.h> +#include <soc/smbus.h> +#include <soc/pmc.h> + +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint16_t tco1_sts; + uint16_t tco2_sts; + uint32_t gpe0_sts[4]; + uint32_t gpe0_en[4]; + uint32_t gen_pmcon_a; + uint32_t gen_pmcon_b; + uint32_t gblrst_cause[2]; + uint32_t hpr_cause0; + uint32_t prev_sleep_state; +} __packed; + +/* Get base address PMC memory mapped registers. */ +uint8_t *pmc_mmio_regs(void); + +/* Get base address of TCO I/O registers. */ +uint16_t smbus_tco_regs(void); + +/* Set the DISB after DRAM init */ +void pmc_set_disb(void); + +/* STM Support */ +uint16_t get_pmbase(void); +#endif /* !defined(__ACPI__) */ + +#endif /* _SOC_PANTHERLAKE_PM_H_ */ diff --git a/src/soc/intel/pantherlake/include/soc/smbus.h b/src/soc/intel/pantherlake/include/soc/smbus.h new file mode 100644 index 0000000000..78a8b9987f --- /dev/null +++ b/src/soc/intel/pantherlake/include/soc/smbus.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PANTHERLAKE_SMBUS_H_ +#define _SOC_PANTHERLAKE_SMBUS_H_ + +#include <intelpch/smbus.h> + +#endif /* _SOC_PANTHERLAKE_SMBUS_H_ */ diff --git a/src/soc/intel/pantherlake/include/soc/soc_info.h b/src/soc/intel/pantherlake/include/soc/soc_info.h new file mode 100644 index 0000000000..c90eb44fc4 --- /dev/null +++ b/src/soc/intel/pantherlake/include/soc/soc_info.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PANTHERLAKE_SOC_INFO_H_ +#define _SOC_PANTHERLAKE_SOC_INFO_H_ + +uint8_t get_max_usb20_port(void); +uint8_t get_max_usb30_port(void); +uint8_t get_max_tcss_port(void); +uint8_t get_max_tbt_pcie_port(void); +uint8_t get_max_pcie_port(void); +uint8_t get_max_pcie_clock(void); +uint8_t get_max_uart_port(void); +uint8_t get_max_i2c_port(void); +uint8_t get_max_gspi_port(void); + +#endif /* _SOC_PANTHERLAKE_SOC_INFO_H_ */ |