diff options
Diffstat (limited to 'src/soc/intel/meteorlake')
| -rw-r--r-- | src/soc/intel/meteorlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/fsp_params.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/romstage/fsp_params.c | 4 |
3 files changed, 8 insertions, 1 deletions
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 79a51baea1..6b40b6698f 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -28,6 +28,7 @@ config CPU_SPECIFIC_OPTIONS select GENERIC_GPIO_LIB select HAVE_DEBUG_RAM_SETUP select HAVE_FSP_GOP + select HAVE_INTEL_COMPLIANCE_TEST_MODE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select INTEL_CAR_NEM diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index ad6d4bb092..53220ec96b 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -375,9 +375,11 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, get_l1_substate_control(rp_cfg->PcieRpL1Substates); s_cfg->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); - s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG); + s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG) + || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); } + s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); } static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 7453eb0222..d104cb3bc1 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -31,6 +31,10 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, static unsigned int clk_req_mapping = 0; for (i = 0; i < cfg_count; i++) { + if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) { + m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING; + continue; + } if (!(en_mask & BIT(i))) continue; if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED) |