diff options
Diffstat (limited to 'src/soc/intel/meteorlake')
| -rw-r--r-- | src/soc/intel/meteorlake/romstage/fsp_params.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 9734c63d5f..055fec7fad 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -52,10 +52,12 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, printk(BIOS_WARNING, "Missing root port clock structure definition\n"); continue; } - if (clk_req_mapping & (1 << cfg[i].clk_req)) - printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n" - , cfg[i].clk_req); + if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) { + if (clk_req_mapping & (1 << cfg[i].clk_req)) + printk(BIOS_WARNING, + "Found overlapped clkreq assignment on clk req %d\n", + cfg[i].clk_req); m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; clk_req_mapping |= 1 << cfg[i].clk_req; } |