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-rw-r--r--src/soc/intel/jasperlake/Kconfig1
-rw-r--r--src/soc/intel/jasperlake/fsp_params.c10
2 files changed, 6 insertions, 5 deletions
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index b2c2dc4288..a05cd72a82 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -60,6 +60,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_RESET
+ select SOC_INTEL_CSE_SET_EOP
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_MONOTONIC_TIMER
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index 0de02f28c6..5f33a3b055 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -23,9 +23,9 @@
* 2 - Send in DXE (Not applicable for FSP in API mode)
*/
enum {
- EOP_DISABLE,
- EOP_PEI,
- EOP_DXE,
+ EOP_DISABLE = 0,
+ EOP_PEI = 1,
+ EOP_DXE = 2,
} EndOfPost;
static void parse_devicetree(FSP_S_CONFIG *params)
@@ -81,8 +81,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->RtcMemoryLock = 1;
}
- /* Enable End of Post in PEI phase */
- params->EndOfPostMessage = EOP_PEI;
+ /* coreboot will send EOP before loading payload */
+ params->EndOfPostMessage = EOP_DISABLE;
/* Legacy 8254 timer support */
params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);