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-rw-r--r--src/soc/intel/jasperlake/include/soc/pcie_modphy.h24
1 files changed, 24 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/include/soc/pcie_modphy.h b/src/soc/intel/jasperlake/include/soc/pcie_modphy.h
new file mode 100644
index 0000000000..60f145195f
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/pcie_modphy.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_JASPERLAKE_PCIE_MODPHY_H_
+#define _SOC_JASPERLAKE_PCIE_MODPHY_H_
+
+struct pcie_modphy_config {
+ /* TX Output Downscale Amplitude Adjustment */
+ bool tx_gen1_downscale_amp_override;
+ uint8_t tx_gen1_downscale_amp;
+ /* TX Output Downscale Amplitude Adjustment */
+ bool tx_gen2_downscale_amp_override;
+ uint8_t tx_gen2_downscale_amp;
+ /* TX Output Downscale Amplitude Adjustment */
+ bool tx_gen3_downscale_amp_override;
+ uint8_t tx_gen3_downscale_amp;
+ /* TX Output -3.5dB Mode De-Emphasis Adjustment Setting */
+ uint8_t tx_gen1_de_emph;
+ /* TX Output -3.5dB Mode De-Emphasis Adjustment Setting */
+ uint8_t tx_gen2_de_emph_3p5;
+ /* TX Output -6.0dB Mode De-Emphasis Adjustment Setting */
+ uint8_t tx_gen2_de_emph_6p0;
+};
+
+#endif