1 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index f3e7240b57..398fe71699 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -421,6 +421,19 @@ struct soc_intel_jasperlake_config {
 		CD_CLOCK_652_8_MHZ = 9,
 	} cd_clock;
 
+	/*
+	 * This is a workaround to mitigate higher SoC power consumption in S0ix
+	 * when the CNVI has background activity.
+	 *
+	 * Setting this on a system that supports S0i3 (set xtalsdqdis [Bit 22] in
+	 * cppmvric1 register to 0) will break CNVI timing.
+	 * Affected Intel wireless chipsets: AC9560 (JfP2), AC9461/AC9462 (JfP1) and
+	 * AX201 (HrP2)
+	 *
+	 * true: Enabled (fewer wakes, lower power)
+	 * false: Disabled (more wakes, higher power)
+	 */
+	bool cnvi_reduce_s0ix_pwr_usage;
 };
 
 typedef struct soc_intel_jasperlake_config config_t;