diff options
Diffstat (limited to 'src/soc/intel/jasperlake/bootblock')
| -rw-r--r-- | src/soc/intel/jasperlake/bootblock/cpu.c | 8 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/bootblock/pch.c | 30 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/bootblock/report_platform.c | 60 |
3 files changed, 4 insertions, 94 deletions
diff --git a/src/soc/intel/jasperlake/bootblock/cpu.c b/src/soc/intel/jasperlake/bootblock/cpu.c index dddf24352d..561172b2ae 100644 --- a/src/soc/intel/jasperlake/bootblock/cpu.c +++ b/src/soc/intel/jasperlake/bootblock/cpu.c @@ -12,19 +12,13 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 6 - */ - #include <intelblocks/fast_spi.h> #include <soc/bootblock.h> void bootblock_cpu_init(void) { /* - * Tigerlake platform doesn't support booting from any other media + * Jasperlake platform doesn't support booting from any other media * (like eMMC on APL/GLK platform) than only booting from SPI device * and on IA platform SPI is memory mapped hence enabling temporarily * cacheing on memory-mapped spi boot media. diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c index b0646018c6..c98fdc5fb6 100644 --- a/src/soc/intel/jasperlake/bootblock/pch.c +++ b/src/soc/intel/jasperlake/bootblock/pch.c @@ -12,12 +12,6 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Processor PCH Datasheet - * Document number: 575857 - * Chapter number: 2, 3, 4, 27, 28 - */ - #include <console/console.h> #include <console/post_codes.h> #include <device/mmio.h> @@ -39,8 +33,8 @@ #include <soc/pcr_ids.h> #include <soc/pm.h> -#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP 0x1100 -#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP 0xA00 +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0xA00 + #define PCR_PSFX_TO_SHDW_BAR0 0 #define PCR_PSFX_TO_SHDW_BAR1 0x4 #define PCR_PSFX_TO_SHDW_BAR2 0x8 @@ -60,20 +54,6 @@ #define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOE 0x2774 -static uint32_t get_pmc_reg_base(void) -{ - uint8_t pch_series; - - pch_series = get_pch_series(); - - if (pch_series == PCH_TGP) - return PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP; - else if (pch_series == PCH_JSP) - return PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP; - else - return 0; -} - static void soc_config_pwrmbase(void) { uint32_t reg32; @@ -116,11 +96,7 @@ void bootblock_pch_early_init(void) static void soc_config_acpibase(void) { uint32_t pmc_reg_value; - uint32_t pmc_base_reg; - - pmc_base_reg = get_pmc_reg_base(); - if (!pmc_base_reg) - die_with_post_code(POST_HW_INIT_FAILURE, "Invalid PMC base address\n"); + uint32_t pmc_base_reg = PCR_PSF3_TO_SHDW_PMC_REG_BASE; pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); diff --git a/src/soc/intel/jasperlake/bootblock/report_platform.c b/src/soc/intel/jasperlake/bootblock/report_platform.c index d7b2e0db32..35f2d1aead 100644 --- a/src/soc/intel/jasperlake/bootblock/report_platform.c +++ b/src/soc/intel/jasperlake/bootblock/report_platform.c @@ -12,12 +12,6 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Platform Stepping and IDs - * Document number: 605534 - * Chapter number: 2, 4, 5, 6 - */ - #include <arch/cpu.h> #include <device/pci_ops.h> #include <console/console.h> @@ -36,7 +30,6 @@ static struct { u32 cpuid; const char *name; } cpu_table[] = { - { CPUID_TIGERLAKE_A0, "Tigerlake A0" }, { CPUID_JASPERLAKE_A0, "Jasperlake A0" }, }; @@ -44,75 +37,22 @@ static struct { u16 mchid; const char *name; } mch_table[] = { - { PCI_DEVICE_ID_INTEL_TGL_ID_U, "Tigerlake-U-4-2" }, - { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" }, - { PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, "Tigerlake-U-2-2" }, - { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" }, { PCI_DEVICE_ID_INTEL_JSL_ID_1, "Jasperlake-1" }, - { PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" }, - { PCI_DEVICE_ID_INTEL_EHL_ID_1, "Elkhartlake-1" }, }; static struct { u16 espiid; const char *name; } pch_table[] = { - { PCI_DEVICE_ID_INTEL_TGP_ESPI_0, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_SUPER_U_ESPI, "Tigerlake-U Super SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_PREMIUM_U_ESPI, "Tigerlake-U Premium SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_BASE_U_ESPI, "Tigerlake-U Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_1, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_2, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_SUPER_Y_ESPI, "Tigerlake-Y Super SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_PREMIUM_Y_ESPI, "Tigerlake-Y Premium SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_3, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_4, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_5, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_6, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_7, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_8, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_9, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_10, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_11, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_12, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_13, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_14, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_15, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_16, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_17, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_18, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_19, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_20, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_21, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_22, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_23, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_24, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_25, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_TGP_ESPI_26, "Tigerlake-Base SKU" }, { PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI, "Jasperlake Super" }, - { PCI_DEVICE_ID_INTEL_MCC_ESPI_0, "Elkhartlake-0" }, - { PCI_DEVICE_ID_INTEL_MCC_ESPI_1, "Elkhartlake-1" }, - { PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI, "Elkhartlake Base" }, - { PCI_DEVICE_ID_INTEL_MCC_PREMIUM_ESPI, "Elkhartlake Premium" }, - { PCI_DEVICE_ID_INTEL_MCC_SUPER_ESPI, "Elkhartlake Super" }, }; static struct { u16 igdid; const char *name; } igd_table[] = { - { PCI_DEVICE_ID_INTEL_TGL_GT0, "Tigerlake U GT0" }, - { PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, "Tigerlake U GT2" }, - { PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, "Tigerlake Y GT2" }, - { PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, "Tigerlake U GT3" }, { PCI_DEVICE_ID_INTEL_JSL_GT1, "Jasperlake GT1" }, { PCI_DEVICE_ID_INTEL_JSL_GT2, "Jasperlake GT2" }, - { PCI_DEVICE_ID_INTEL_EHL_GT1_1, "Elkhartlake GT1 1" }, - { PCI_DEVICE_ID_INTEL_EHL_GT2_1, "Elkhartlake GT2 1" }, - { PCI_DEVICE_ID_INTEL_EHL_GT1_2, "Elkhartlake GT1 2" }, - { PCI_DEVICE_ID_INTEL_EHL_GT2_2, "Elkhartlake GT2 2" }, - { PCI_DEVICE_ID_INTEL_EHL_GT1_3, "Elkhartlake GT1 3" }, - { PCI_DEVICE_ID_INTEL_EHL_GT2_3, "Elkhartlake GT2 3" }, }; static inline uint8_t get_dev_revision(pci_devfn_t dev) |