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-rw-r--r--src/soc/intel/icelake/Kconfig1
-rw-r--r--src/soc/intel/icelake/include/soc/pm.h3
-rw-r--r--src/soc/intel/icelake/pmutil.c14
3 files changed, 1 insertions, 17 deletions
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index ae693a4c4f..d8845513b6 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -56,6 +56,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_RESET
+ select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_MONOTONIC_TIMER
diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h
index ad2beff0e0..05db830b37 100644
--- a/src/soc/intel/icelake/include/soc/pm.h
+++ b/src/soc/intel/icelake/include/soc/pm.h
@@ -155,9 +155,6 @@ uint16_t smbus_tco_regs(void);
/* Set the DISB after DRAM init */
void pmc_set_disb(void);
-/* Clear PMCON status bits */
-void pmc_clear_pmcon_sts(void);
-
/* STM Support */
uint16_t get_pmbase(void);
diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c
index f552a8c8e5..b7829b22b7 100644
--- a/src/soc/intel/icelake/pmutil.c
+++ b/src/soc/intel/icelake/pmutil.c
@@ -126,20 +126,6 @@ void pmc_set_disb(void)
write8(addr, disb_val);
}
-void pmc_clear_pmcon_sts(void)
-{
- uint32_t reg_val;
- uint8_t *addr;
- addr = pmc_mmio_regs();
-
- reg_val = read32(addr + GEN_PMCON_A);
- /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
- * while retaining MS4V write-1-to-clear bit */
- reg_val &= ~(MS4V);
-
- write32((addr + GEN_PMCON_A), reg_val);
-}
-
/*
* PMC controller gets hidden from PCI bus
* during FSP-Silicon init call. Hence PWRMBASE