diff options
Diffstat (limited to 'src/soc/intel/icelake')
| -rw-r--r-- | src/soc/intel/icelake/bootblock/pch.c | 18 | ||||
| -rw-r--r-- | src/soc/intel/icelake/espi.c | 24 |
2 files changed, 2 insertions, 40 deletions
diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 08edfeec16..18e611962b 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -33,9 +33,6 @@ #define PCR_DMI_PMBASEA 0x27AC #define PCR_DMI_PMBASEC 0x27B0 -#define PCR_DMI_LPCIOD 0x2770 -#define PCR_DMI_LPCIOE 0x2774 - static void soc_config_pwrmbase(void) { /* @@ -120,19 +117,8 @@ void pch_early_iorange_init(void) lpc_io_setup_comm_a_b(); /* IO Decode Enable */ - if (pch_check_decode_enable() == 0) { - io_enables = lpc_enable_fixed_io_ranges(io_enables); - /* - * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same - * value programmed in ESPI PCI offset 82h. - */ - pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); - /* - * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same - * value programmed in LPC PCI offset 80h. - */ - pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); - } + if (pch_check_decode_enable() == 0) + lpc_enable_fixed_io_ranges(io_enables); /* Program generic IO Decode Range */ pch_enable_lpc(); diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index fdcd83357e..489fe34223 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -9,7 +9,6 @@ #include <arch/ioapic.h> #include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> -#include <intelblocks/pcr.h> #include <soc/espi.h> #include <soc/iomap.h> #include <soc/irq.h> @@ -27,29 +26,7 @@ void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) gen_io_dec[3] = config->gen4_dec; } -void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) -{ - /* Mirror these same settings in DMI PCR */ - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); -} - #if ENV_RAMSTAGE -static void soc_mirror_dmi_pcr_io_dec(void) -{ - struct device *dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 0); - uint32_t io_dec_arr[] = { - pci_read_config32(dev, ESPI_GEN1_DEC), - pci_read_config32(dev, ESPI_GEN2_DEC), - pci_read_config32(dev, ESPI_GEN3_DEC), - pci_read_config32(dev, ESPI_GEN4_DEC), - }; - /* Mirror these same settings in DMI PCR */ - soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); -} - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ @@ -70,7 +47,6 @@ void lpc_soc_init(struct device *dev) pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); - soc_mirror_dmi_pcr_io_dec(); } /* Fill up ESPI IO resource structure inside SoC directory */ |