diff options
Diffstat (limited to 'src/soc/intel/icelake/romstage/fsp_params.c')
-rw-r--r-- | src/soc/intel/icelake/romstage/fsp_params.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c new file mode 100644 index 0000000000..69b5b7a7ad --- /dev/null +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/util.h> +#include <soc/romstage.h> + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + /* ToDo: update with UPD override as FSP matures */ +} + +__weak void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} |