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Diffstat (limited to 'src/soc/intel/icelake/acpi')
-rw-r--r--src/soc/intel/icelake/acpi/cnvi.asl32
-rw-r--r--src/soc/intel/icelake/acpi/southbridge.asl3
2 files changed, 0 insertions, 35 deletions
diff --git a/src/soc/intel/icelake/acpi/cnvi.asl b/src/soc/intel/icelake/acpi/cnvi.asl
deleted file mode 100644
index 634c6090ad..0000000000
--- a/src/soc/intel/icelake/acpi/cnvi.asl
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <soc/pm.h>
-
-/* CNVi Controller 0:14.3 */
-Device (CNVI) {
- Name(_ADR, 0x00140003)
-
- Name (_S3D, 3) /* D3 supported in S3 */
- Name (_S0W, 3) /* D3 can wake device in S0 */
- Name (_S3W, 3) /* D3 can wake system from S3 */
-
- Name (_PRW, Package() { PME_B0_EN_BIT, 3 })
-
- Method (_STA, 0)
- {
- Return (0xF)
- }
-}
diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl
index ff323c40a3..5cdc940523 100644
--- a/src/soc/intel/icelake/acpi/southbridge.asl
+++ b/src/soc/intel/icelake/acpi/southbridge.asl
@@ -56,8 +56,5 @@
/* PCI _OSC */
#include <soc/intel/common/acpi/pci_osc.asl>
-/* CNVi */
-#include "cnvi.asl"
-
/* GBe 0:1f.6 */
#include "pch_glan.asl"