diff options
Diffstat (limited to 'src/soc/intel/icelake/Kconfig')
| -rw-r--r-- | src/soc/intel/icelake/Kconfig | 205 |
1 files changed, 0 insertions, 205 deletions
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig deleted file mode 100644 index aca73faae9..0000000000 --- a/src/soc/intel/icelake/Kconfig +++ /dev/null @@ -1,205 +0,0 @@ -config SOC_INTEL_ICELAKE - bool - help - Intel Icelake support - -if SOC_INTEL_ICELAKE - -config CPU_SPECIFIC_OPTIONS - def_bool y - select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_X86 - select BOOT_DEVICE_SUPPORTS_WRITES - select CACHE_MRC_SETTINGS - select SET_IA32_FC_LOCK_BIT - select CPU_INTEL_FIRMWARE_INTERFACE_TABLE - select CPU_SUPPORTS_PM_TIMER_EMULATION - select DISPLAY_FSP_VERSION_INFO - select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 - select FSP_M_XIP - select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 - select GENERIC_GPIO_LIB - select HAVE_FSP_GOP - select HAVE_INTEL_FSP_REPO - select INTEL_DESCRIPTOR_MODE_CAPABLE - select HAVE_SMI_HANDLER - select IDT_IN_EVERY_STAGE - select INTEL_CAR_NEM_ENHANCED - select INTEL_GMA_ACPI - select INTEL_GMA_ADD_VBT if RUN_FSP_GOP - select MP_SERVICES_PPI_V1 - select MRC_SETTINGS_PROTECT - select PARALLEL_MP_AP_WORK - select MICROCODE_BLOB_UNDISCLOSED - select PLATFORM_USES_FSP2_1 - select PMC_GLOBAL_RESET_ENABLE_LOCK - select CPU_INTEL_COMMON - select SOC_INTEL_COMMON - select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE - select SOC_INTEL_COMMON_BLOCK - select SOC_INTEL_COMMON_BLOCK_ACPI - select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC - select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT - select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO - select SOC_INTEL_COMMON_BLOCK_CAR - select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG - select SOC_INTEL_COMMON_BLOCK_CNVI - select SOC_INTEL_COMMON_BLOCK_CPU - select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT - select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE - select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 - select SOC_INTEL_COMMON_BLOCK_HDA - select SOC_INTEL_COMMON_BLOCK_SA - select SOC_INTEL_COMMON_BLOCK_SCS - select SOC_INTEL_COMMON_BLOCK_SMM - select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP - select SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV - select SOC_INTEL_COMMON_FSP_RESET - select SOC_INTEL_COMMON_PCH_CLIENT - select SOC_INTEL_COMMON_RESET - select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION - select SSE2 - select SUPPORT_CPU_UCODE_IN_CBFS - select TSC_MONOTONIC_TIMER - select UDELAY_TSC - select UDK_2017_BINDING - select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM - select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT - select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE - select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI - -config DISABLE_HECI1_AT_PRE_BOOT - default y if MAINBOARD_HAS_CHROMEOS - select HECI_DISABLE_USING_SMM - -config DCACHE_RAM_BASE - default 0xfef00000 - -config DCACHE_RAM_SIZE - default 0x40000 - help - The size of the cache-as-ram region required during bootblock - and/or romstage. - -config DCACHE_BSP_STACK_SIZE - hex - default 0x20400 - help - The amount of anticipated stack usage in CAR by bootblock and - other stages. In the case of FSP_USES_CB_STACK default value will be - sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB). - -config FSP_TEMP_RAM_SIZE - hex - default 0x10000 - help - The amount of anticipated heap usage in CAR by FSP. - Refer to Platform FSP integration guide document to know - the exact FSP requirement for Heap setup. - -config IFD_CHIPSET - string - default "icl" - -config IED_REGION_SIZE - hex - default 0x400000 - -config HEAP_SIZE - hex - default 0x8000 - -config MAX_ROOT_PORTS - int - default 16 - -config SMM_TSEG_SIZE - hex - default 0x800000 - -config SMM_RESERVED_SIZE - hex - default 0x200000 - -config PCR_BASE_ADDRESS - hex - default 0xfd000000 - help - This option allows you to select MMIO Base Address of sideband bus. - -config ECAM_MMCONF_BASE_ADDRESS - default 0xc0000000 - -config CPU_BCLK_MHZ - int - default 100 - -config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ - int - default 120 - -config CPU_XTAL_HZ - default 38400000 - -config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ - int - default 133 - -config SOC_INTEL_COMMON_BLOCK_GSPI_MAX - int - default 3 - -config SOC_INTEL_I2C_DEV_MAX - int - default 6 - -config SOC_INTEL_UART_DEV_MAX - int - default 3 - -config CONSOLE_UART_BASE_ADDRESS - hex - default 0xfe032000 - depends on INTEL_LPSS_UART_FOR_CONSOLE - -# Clock divider parameters for 115200 baud rate -config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL - hex - default 0x30 - -config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL - hex - default 0xc35 - -config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_VBNV_CMOS - select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH - -config CBFS_SIZE - default 0x200000 - -config FSP_HEADER_PATH - default "3rdparty/fsp/IceLakeFspBinPkg/Include" - -config FSP_FD_PATH - default "3rdparty/fsp/IceLakeFspBinPkg/Fsp.fd" - -config SOC_INTEL_ICELAKE_DEBUG_CONSENT - int "Debug Consent for ICL" - # USB DBC is more common for developers so make this default to 3 if - # SOC_INTEL_DEBUG_CONSENT=y - default 3 if SOC_INTEL_DEBUG_CONSENT - default 0 - help - This is to control debug interface on SOC. - Setting non-zero value will allow to use DBC or DCI to debug SOC. - PlatformDebugConsent in FspmUpd.h has the details. - - Desired platform debug types are - 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), - 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), - 6:Enable (2-wire DCI OOB), 7:Manual - -endif |