diff options
Diffstat (limited to 'src/soc/intel/fsp_broadwell_de/include')
16 files changed, 0 insertions, 998 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h b/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h deleted file mode 100644 index 419f229938..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2015-2016 Intel Corp. - * Copyright (C) 2016-2018 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_ACPI_H_ -#define _SOC_ACPI_H_ - -#include <arch/acpi.h> - -void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt); -unsigned long acpi_madt_irq_overrides(unsigned long current); -uint16_t get_pmbase(void); -unsigned long vtd_write_acpi_tables(struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp); -unsigned long southcluster_write_acpi_tables(struct device *device, - unsigned long start, - acpi_rsdp_t *rsdp); -#endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h deleted file mode 100644 index a44b857c1f..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2015-2016 Intel Corp. - * Copyright (C) 2017-2018 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_BROADWELL_DE_H_ -#define _SOC_BROADWELL_DE_H_ - -uintptr_t sa_get_tseg_base(void); -size_t sa_get_tseg_size(void); - -#define VTBAR_OFFSET 0x180 -#define VTBAR_MASK 0xffffe000 -#define VTBAR_ENABLED 0x01 -#define VTBAR_SIZE 0x2000 - -#define SMM_FEATURE_CONTROL 0x58 -#define SMM_CPU_SAVE_EN (1 << 1) -#define TSEG_BASE 0xa8 /* TSEG base */ -#define TSEG_LIMIT 0xac /* TSEG limit */ - -#define IIO_LTDPR 0x290 -#define DPR_LOCK (1 << 0) -#define DPR_EPM (1 << 2) -#define DPR_PRS (1 << 1) -#define DPR_SIZE_MASK 0xff0 -#define DPR_SIZE_SHIFT 4 -#define DPR_ADDR_MASK 0xfff00000 -#define DPR_ADDR_SHIFT 20 - -/* CPU bus clock is fixed at 100MHz */ -#define CPU_BCLK 100 - -#endif /* _SOC_BROADWELL_DE_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/gpio.h b/src/soc/intel/fsp_broadwell_de/include/soc/gpio.h deleted file mode 100644 index 1159d03910..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/gpio.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef FSP_BROADWELL_DE_GPIO_H_ -#define FSP_BROADWELL_DE_GPIO_H_ - -#include <stdint.h> - -/* Chipset owned GPIO configuration registers */ -#define GPIO_1_USE_SEL 0x00 -#define GPIO_1_IO_SEL 0x04 -#define GPIO_1_LVL 0x0c -#define GPIO_1_BLINK 0x18 -#define GPIO_1_NMI_EN 0x28 -#define GPIO_1_INVERT 0x2c -#define GPIO_2_USE_SEL 0x30 -#define GPIO_2_IO_SEL 0x34 -#define GPIO_2_LVL 0x38 -#define GPIO_2_NMI_EN 0x3c -#define GPIO_3_USE_SEL 0x40 -#define GPIO_3_IO_SEL 0x44 -#define GPIO_3_LVL 0x48 -#define GPIO_3_NMI_EN 0x50 -#define REG_INVALID 0xff - -/* The pin can either be a GPIO or connected to the native function. */ -#define GPIO_MODE_NATIVE 0 -#define GPIO_MODE_GPIO 1 -/* Once configured as GPIO the pin can be an input or an output. */ -#define GPIO_OUTPUT 0 -#define GPIO_INPUT 1 -#define GPIO_NMI_EN 1 -/* For output GPIO mode the pin can either drive high or low level. */ -#define GPIO_OUT_LEVEL_LOW 0 -#define GPIO_OUT_LEVEL_HIGH 1 -/* The following functions are only valid for GPIO bank 1. */ -#define GPIO_OUT_BLINK 1 -#define GPIO_IN_INVERT 1 - -#define GPIO_NUM_BANKS 3 -#define MAX_GPIO_NUM 75 /* 0 based GPIO number */ -#define GPIO_LIST_END 0xff - -/* Define possible GPIO configurations. */ -#define PCH_GPIO_END \ - { .use_sel = GPIO_LIST_END } - -#define PCH_GPIO_NATIVE(gpio) { \ - .num = (gpio), \ - .use_sel = GPIO_MODE_NATIVE } - -#define PCH_GPIO_INPUT(gpio) { \ - .num = (gpio), \ - .use_sel = GPIO_MODE_GPIO, \ - .io_sel = GPIO_INPUT } - -#define PCH_GPIO_INPUT_INVERT(gpio) { \ - .num = (gpio), \ - .use_sel = GPIO_MODE_GPIO, \ - .io_sel = GPIO_INPUT, \ - .invert_input = GPIO_IN_INVERT } - -#define PCH_GPIO_INPUT_NMI(gpio) { \ - .num = (gpio), \ - .use_sel = GPIO_MODE_GPIO, \ - .io_sel = GPIO_INPUT, \ - .nmi_en = GPIO_NMI_EN } - -#define PCH_GPIO_OUT_LOW(gpio) { \ - .num = (gpio), \ - .use_sel = GPIO_MODE_GPIO, \ - .io_sel = GPIO_OUTPUT, \ - .level = GPIO_OUT_LEVEL_LOW } - -#define PCH_GPIO_OUT_HIGH(gpio) { \ - .num = (gpio), \ - .use_sel = GPIO_MODE_GPIO, \ - .io_sel = GPIO_OUTPUT, \ - .level = GPIO_OUT_LEVEL_HIGH } - -#define PCH_GPIO_OUT_BLINK(gpio) { \ - .num = (gpio), \ - .use_sel = GPIO_MODE_GPIO, \ - .io_sel = GPIO_OUTPUT, \ - .blink_en = GPIO_OUT_BLINK } - -struct gpio_config { - uint8_t num; - uint8_t use_sel; - uint8_t io_sel; - uint8_t level; - uint8_t blink_en; - uint8_t nmi_en; - uint8_t invert_input; -} __packed; - -/* Unfortunately the register layout is not linear between different GPIO banks. - * In addition not every bank has all the functions so that some registers might - * be missing on a particular bank. To make the code better readable introduce a - * wrapper structure for the register addresses for every bank. - */ -struct gpio_config_regs { - uint8_t use_sel; - uint8_t io_sel; - uint8_t level; - uint8_t nmi_en; - uint8_t blink_en; - uint8_t invert_input; -}; - -/* Define gpio_t here to be able to use src/include/gpio.h for gpio_set() and - gpio_get().*/ -typedef uint8_t gpio_t; - -/* Configure GPIOs with mainboard provided settings */ -void init_gpios(const struct gpio_config config[]); - -#endif /* FSP_BROADWELL_DE_GPIO_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/iomap.h b/src/soc/intel/fsp_broadwell_de/include/soc/iomap.h deleted file mode 100644 index ac04c63af7..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/iomap.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_IOMAP_H_ -#define _SOC_IOMAP_H_ - -/* - * Memory Mapped IO bases. - */ - -/* PCI Configuration Space */ -#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS -#define MCFG_BASE_SIZE 0x10000000 - -/* Transactions in this range will abort */ -#define ABORT_BASE_ADDRESS 0xfeb00000 -#define ABORT_BASE_SIZE 0x00010000 - -/* PSEG */ -#define PSEG_BASE_ADDRESS 0xfeb80000 -#define PSEG_BASE_SIZE 0x00080000 - -/* IOxAPIC */ -#define IOXAPIC1_BASE_ADDRESS 0xfec00000 -#define IOXAPIC1_BASE_SIZE 0x00100000 -#define IOXAPIC2_BASE_ADDRESS 0xfec01000 -#define IOXAPIC2_BASE_SIZE 0x00100000 - -/* PCH (HPET/LT/TPM/Others) */ -#define PCH_BASE_ADDRESS 0xfed00000 -#define PCH_BASE_SIZE 0x00100000 - -/* Local XAPIC */ -#define LXAPIC_BASE_ADDRESS 0xfee00000 -#define LXAPIC_BASE_SIZE 0x00100000 - -/* High Performance Event Timer */ -#define HPET_BASE_ADDRESS 0xfed00000 -#define HPET_BASE_SIZE 0x400 - -/* Firmware */ -#define FIRMWARE_BASE_ADDRESS 0xff000000 -#define FIRMWARE_BASE_SIZE 0x01000000 - -/* - * IO Port bases. - */ - -/* ACPI Base Address */ -#define ACPI_BASE_ADDRESS 0x400 -#define ACPI_BASE_SIZE 0x80 - -/* GPIO Base Address */ -#define GPIO_BASE_ADDRESS 0x500 -#define GPIO_BASE_SIZE 0x80 - -#endif /* _SOC_IOMAP_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/irq.h b/src/soc/intel/fsp_broadwell_de/include/soc/irq.h deleted file mode 100644 index 1344f3b880..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/irq.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_IRQ_H_ -#define _SOC_IRQ_H_ - -#define PIRQA_APIC_IRQ 16 -#define PIRQB_APIC_IRQ 17 -#define PIRQC_APIC_IRQ 18 -#define PIRQD_APIC_IRQ 19 -#define PIRQE_APIC_IRQ 20 -#define PIRQF_APIC_IRQ 21 -#define PIRQG_APIC_IRQ 22 -#define PIRQH_APIC_IRQ 23 - -/* PIC IRQ settings. */ -#define PIRQ_PIC_IRQ3 0x3 -#define PIRQ_PIC_IRQ4 0x4 -#define PIRQ_PIC_IRQ5 0x5 -#define PIRQ_PIC_IRQ6 0x6 -#define PIRQ_PIC_IRQ7 0x7 -#define PIRQ_PIC_IRQ9 0x9 -#define PIRQ_PIC_IRQ10 0xa -#define PIRQ_PIC_IRQ11 0xb -#define PIRQ_PIC_IRQ12 0xc -#define PIRQ_PIC_IRQ14 0xe -#define PIRQ_PIC_IRQ15 0xf -#define PIRQ_PIC_IRQDISABLE 0x80 -#define PIRQ_PIC_UNKNOWN_UNUSED 0xff - -/* Overloaded term, but these values determine the per device route. */ -#define PIRQA 0 -#define PIRQB 1 -#define PIRQC 2 -#define PIRQD 3 -#define PIRQE 4 -#define PIRQF 5 -#define PIRQG 6 -#define PIRQH 7 - -#define ACPI_CNTL_OFFSET 0x44 -#define SCIS_MASK 0x07 -#define SCIS_IRQ9 0x00 -#define SCIS_IRQ10 0x01 -#define SCIS_IRQ11 0x02 -#define SCIS_IRQ20 0x04 -#define SCIS_IRQ21 0x05 -#define SCIS_IRQ22 0x06 -#define SCIS_IRQ23 0x07 - -/* In each mainboard directory there should exist a header file irqroute.h that - * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which - * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */ - -#if !defined(__ASSEMBLER__) && !defined(__ACPI__) -#include <stdint.h> - -#define NUM_OF_PCI_DEVS 32 -#define NUM_PIRQS 8 - -struct broadwell_de_irq_route { - /* Per device configuration. */ - uint16_t pcidev[NUM_OF_PCI_DEVS]; - /* Route path for each internal PIRQx in PIC mode. */ - uint8_t pic[NUM_PIRQS]; -}; - -extern const struct broadwell_de_irq_route global_broadwell_de_irq_route; - -#define DEFINE_IRQ_ROUTES \ - const struct broadwell_de_irq_route global_broadwell_de_irq_route = { \ - .pcidev = { PCI_DEV_PIRQ_ROUTES, }, \ - .pic = { PIRQ_PIC_ROUTES, }, \ - } - -#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ - [dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \ - ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0) - -#define PIRQ_PIC(pirq_, pic_irq_) \ - [PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_ - -#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ - -#endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h b/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h deleted file mode 100644 index 3f9c2024f7..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_LPC_H_ -#define _SOC_LPC_H_ - -#include <arch/acpi.h> - -/* LPC Interface Bridge PCI Configuration Registers */ -#define GPIO_BASE_ADR_OFFSET 0x48 -#define GPIO_CTRL_OFFSET 0x4c -#define GPIO_DECODE_ENABLE (1 << 4) -#define REVID 0x08 -#define PIRQ_RCR1 0x60 -#define SIRQ_CNTL 0x64 -#define SIRQ_EN 0x80 -#define SIRQ_MODE_QUIET 0x00 -#define SIRQ_MODE_CONT 0x40 -#define PIRQ_RCR2 0x68 -#define LPC_IO_DEC 0x80 -#define LPC_EN 0x82 -#define LPC_GEN1_DEC 0x84 -#define LPC_GEN2_DEC 0x88 -#define LPC_GEN3_DEC 0x8c -#define LPC_GEN4_DEC 0x90 -#define GEN_PMCON_1 0xA0 -#define SMI_LOCK (1 << 4) -#define SMI_LOCK_GP6 (1 << 5) -#define SMI_LOCK_GP22 (1 << 6) -#define GEN_PMCON_2 0xA2 -#define GEN_PMCON_3 0xA4 -#define RTC_PWR_STS (1 << 2) - -/* Default IO range claimed by the LPC device. The upper bound is exclusive. */ -#define LPC_DEFAULT_IO_RANGE_LOWER 0 -#define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 - -/* IO Mapped registers behind ACPI_BASE_ADDRESS */ -#define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define USB_STS (1 << 13) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define TMROF_STS (1 << 0) -#define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) -#define PM1_CNT 0x04 -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) -#define PM1_TMR 0x08 -#define GPE0_STS 0x20 -#define PCI_EXP_STS (1 << 9) -#define RI_STS (1 << 8) -#define SMB_WAK_STS (1 << 7) -#define TCOSCI_STS (1 << 6) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) -#define GPE0_EN 0x28 -#define SMI_EN 0x30 -#define XHCI_SMI_EN (1 << 31) -#define ME_SMI_EN (1 << 30) -#define GPIO_UNLOCK_SMI_EN (1 << 27) -#define INTEL_USB2_EN (1 << 18) -#define LEGACY_USB2_EN (1 << 17) -#define PERIODIC_EN (1 << 14) -#define TCO_EN (1 << 13) -#define MCSMI_EN (1 << 11) -#define BIOS_RLS (1 << 7) -#define SWSMI_TMR_EN (1 << 6) -#define APMC_EN (1 << 5) -#define SLP_SMI_EN (1 << 4) -#define LEGACY_USB_EN (1 << 3) -#define BIOS_EN (1 << 2) -#define EOS (1 << 1) -#define GBL_SMI_EN (1 << 0) -#define SMI_STS 0x34 -#define ALT_GPIO_SMI 0x38 -#define UPRWC 0x3c -#define UPRWC_WR_EN (1 << 1) // USB Per-Port Registers Write Enable -#define GPE_CTRL 0x40 -#define PM2A_CNT_BLK 0x50 -#define TCO_RLD 0x60 -#define TCO_STS 0x64 -#define SECOND_TO_STS (1 << 17) -#define TCO_TIMEOUT (1 << 3) -#define TCO1_CNT 0x68 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HALT (1 << 11) -#define TCO_TMR 0x70 - -/* PM1_CNT */ -void enable_pm1_control(uint32_t mask); -void disable_pm1_control(uint32_t mask); - -/* PM1 */ -uint16_t clear_pm1_status(void); -void enable_pm1(uint16_t events); -uint32_t clear_smi_status(void); - -/* SMI */ -void enable_smi(uint32_t mask); -void disable_smi(uint32_t mask); - -#endif /* _SOC_LPC_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/memory.h b/src/soc/intel/fsp_broadwell_de/include/soc/memory.h deleted file mode 100644 index 3bdba2ef56..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/memory.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Facebook, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_MEMORY_H_ -#define _SOC_MEMORY_H_ - -/* EDS vol 2, 9.2.24 */ -#define REG_MC_BIOS_REQ 0x98 -#define REG_MC_BIOS_REQ_FREQ_MSK ((1u << 6) - 1) -#define REG_MC_MULTIPLIER 133.33f - -#define IMC_MAX_CHANNELS 2 - -#define SPD_SLAVE_ADDR(chan, slot) (2 * chan + slot) - -void save_dimm_info(void); - -#endif diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h deleted file mode 100644 index f9fdffb2bf..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2015-2016 Intel Corp. - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_MSR_H_ -#define _SOC_MSR_H_ - -#define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_PLATFORM_INFO 0xce -#define MSR_TURBO_RATIO_LIMIT 0x1ad -#define MSR_PKG_POWER_SKU_UNIT 0x606 -#define MSR_PKG_POWER_LIMIT 0x610 -#define MSR_UNCORE_RATIO_LIMIT 0x620 -#define MSR_CONFIG_TDP_NOMINAL 0x648 - -#define SMM_MCA_CAP_MSR 0x17d -#define SMM_CPU_SVRSTR_BIT 57 -#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) - -/* SMM save state MSRs */ -#define SMBASE_MSR 0xc20 -#define IEDBASE_MSR 0xc22 -/* MTRR_CAP_MSR bits */ -#define SMRR_SUPPORTED (1 << 11) -#define PRMRR_SUPPORTED (1 << 12) -#define MSR_PRMRR_PHYS_BASE 0x1f4 -#define MSR_PRMRR_PHYS_MASK 0x1f5 - -#endif /* _SOC_MSR_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/pattrs.h b/src/soc/intel/fsp_broadwell_de/include/soc/pattrs.h deleted file mode 100644 index 232a4f4a7d..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/pattrs.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_PATTRS_H_ -#define _SOC_PATTRS_H_ - -#include <stdint.h> -#include <cpu/x86/msr.h> - -/* - * The pattrs structure is a common place to stash pertinent information - * about the processor or platform. Instead of going to the source (msrs, cpuid) - * every time an attribute is needed use the pattrs structure. - */ -struct pattrs { - msr_t platform_id; - msr_t platform_info; - uint32_t cpuid; - int revid; - int stepping; - const void *microcode_patch; - int address_bits; - int num_cpus; -}; - -/* - * This is just to hide the abstraction w/o relying on how the underlying - * storage is allocated. - */ -#define PATTRS_GLOB_NAME __global_pattrs -#define DEFINE_PATTRS struct pattrs PATTRS_GLOB_NAME -extern DEFINE_PATTRS; - -static inline const struct pattrs *pattrs_get(void) -{ - return &PATTRS_GLOB_NAME; -} - -#endif /* _SOC_PATTRS_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h deleted file mode 100644 index 6a68b2f81f..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_PCI_DEVS_H_ -#define _SOC_PCI_DEVS_H_ - -#include <device/pci_def.h> - -#define BUS0 0 - -#define SOC_DEV 0 -#define SOC_FUNC 0 - -/* DMI2/PCIe link to PCH */ -#define PCIE_IIO_PORT_0_DEV 0x00 -#define PCIE_IIO_PORT_0_FUNC 0x00 - -/* IOU2, x8 PCIe Gen3 port */ -#define PCIE_IIO_PORT_1_DEV 0x01 -#define PCIE_IIO_PORT_1A_FUNC 0x00 -#define PCIE_IIO_PORT_1B_FUNC 0x01 - -/* IOU0: Internal IOSF bridge to 10 GbE and CBDMA */ -#define PCIE_IIO_PORT_2_DEV 0x02 -#define PCIE_IIO_PORT_2A_FUNC 0x00 -#define PCIE_IIO_PORT_2B_FUNC 0x01 -#define PCIE_IIO_PORT_2C_FUNC 0x02 -#define PCIE_IIO_PORT_2D_FUNC 0x03 - -/* IOU1: x16 PCIe Gen3 port */ -#define PCIE_IIO_PORT_3_DEV 0x03 -#define PCIE_IIO_PORT_3A_FUNC 0x00 -#define PCIE_IIO_PORT_3B_FUNC 0x01 -#define PCIE_IIO_PORT_3C_FUNC 0x02 -#define PCIE_IIO_PORT_3D_FUNC 0x03 - -#define VTD_DEV 5 -#define VTD_FUNC 0 -#define IIO_DEVFN_VTD PCI_DEVFN(VTD_DEV, VTD_FUNC) -#define VTD_PCI_DEV PCI_DEV(BUS0, VTD_DEV, VTD_FUNC) - -#define LPC_DEV 31 -#define LPC_FUNC 0 -#define PCH_DEVFN_LPC PCI_DEVFN(LPC_DEV, LPC_FUNC) - -#define SATA_DEV 31 -#define SATA_FUNC 2 - -#define SMBUS_DEV 31 -#define SMBUS_FUNC 3 - -#define SATA2_DEV 31 -#define SATA2_FUNC 5 - -#define EHCI1_DEV 29 -#define EHCI1_FUNC 0 - -#define EHCI2_DEV 26 -#define EHCI2_FUNC 0 - -#define XHCI_DEV 20 -#define XHCI_FUNC 0 -#define XHCI_FUS_REG 0xE0 -#define XHCI_FUNC_DISABLE (1 << 0) -#define XHCI_USB2PR_REG 0xD0 - -#define GBE_DEV 25 -#define GBE_FUNC 0 - -#define ME_DEV 22 -#define ME_FUNC 0 - -#define HDA_DEV 27 -#define HDA_FUNC 0 - -/* Ports from PCH block with adjustable burification settings */ -#define PCIE_DEV 28 -#define PCIE_PORT1_DEV PCIE_DEV -#define PCIE_PORT1_FUNC 0 -#define PCIE_PORT2_DEV PCIE_DEV -#define PCIE_PORT2_FUNC 1 -#define PCIE_PORT3_DEV PCIE_DEV -#define PCIE_PORT3_FUNC 2 -#define PCIE_PORT4_DEV PCIE_DEV -#define PCIE_PORT4_FUNC 3 -#define PCIE_PORT5_DEV PCIE_DEV -#define PCIE_PORT5_FUNC 4 -#define PCIE_PORT6_DEV PCIE_DEV -#define PCIE_PORT6_FUNC 5 -#define PCIE_PORT7_DEV PCIE_DEV -#define PCIE_PORT7_FUNC 6 -#define PCIE_PORT8_DEV PCIE_DEV -#define PCIE_PORT8_FUNC 7 - -/* The SMM device is located on bus 0xff (QPI) */ -#define QPI_BUS 0xff -#define SMM_DEV 0x10 -#define SMM_FUNC 0x06 - -#define IMC_DEV0 19 -#define IMC_FUNC0 0 - -#define IMC_DEV PCI_DEV(QPI_BUS, IMC_DEV0, IMC_FUNC0) - -#define PCU1_DEV 30 -#define PCU1_FUNC 01 -#define UBOX_DEV 16 -#define UBOX_FUNC 7 - - -#define SOC_DEVID 0x2F00 -#define SOC_DEVID_ES2 0x6F00 -#define VTD_DEVID 0x6f28 -#define LPC_DEVID 0x8C42 -#define LPC_DEVID_ES2 0x8C54 -#define AHCI_DEVID 0x8C02 -#define SMBUS_DEVID 0x8C22 -#define EHCI1_DEVID 0x8C26 -#define EHCI2_DEVID 0x8C2D -#define XHCI_DEVID 0x8C31 -#define GBE_DEVID 0x8C33 -#define ME_DEVID 0x8C3A -#define HDA_DEVID 0x8C20 -#define PCIE_PORT1_DEVID 0x8C10 -#define PCIE_PORT2_DEVID 0x8C12 -#define PCIE_PORT3_DEVID 0x8C14 -#define PCIE_PORT4_DEVID 0x8C16 -#define PCIE_PORT5_DEVID 0x8C18 -#define PCIE_PORT6_DEVID 0x8C1A -#define PCIE_PORT7_DEVID 0x8C1C -#define PCIE_PORT8_DEVID 0x8C1E - -#endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/ramstage.h b/src/soc/intel/fsp_broadwell_de/include/soc/ramstage.h deleted file mode 100644 index 69fb687276..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/ramstage.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_RAMSTAGE_H_ -#define _SOC_RAMSTAGE_H_ - -#include <device/device.h> - -/* The broadwell_de_init_pre_device() function is called prior to device - * initialization, but it's after console and cbmem has been reinitialized. */ -void broadwell_de_init_pre_device(void); -void broadwell_de_init_cpus(struct device *dev); -void southcluster_enable_dev(struct device *dev); -void broadwell_de_set_dpr(const uintptr_t addr, const size_t size); -void broadwell_de_lock_dpr(void); - -extern struct pci_operations soc_pci_ops; - -#endif /* _SOC_RAMSTAGE_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h b/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h deleted file mode 100644 index 6ee160de28..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_ROMSTAGE_H_ -#define _SOC_ROMSTAGE_H_ - -#include <stdint.h> -#include <fsp.h> - -#define NUM_ROMSTAGE_TS 4 - -void early_mainboard_romstage_entry(void); -void late_mainboard_romstage_entry(void); - -#endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smbus.h b/src/soc/intel/fsp_broadwell_de/include/soc/smbus.h deleted file mode 100644 index 4d9d3e1f57..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/smbus.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com> - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BROADWELL_SMBUS_H_ -#define _BROADWELL_SMBUS_H_ - -/* PCI Configuration Space (D31:F3): SMBus */ -#define SMB_BASE 0x20 -#define HOSTC 0x40 -#define HST_EN (1 << 0) -#define SMB_RCV_SLVA 0x09 - -/* SMBus I/O bits. */ -#define SMBHSTSTAT 0x0 -#define SMBHSTCTL 0x2 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBBLKDAT 0x7 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf - -#define SMBUS_TIMEOUT (10 * 1000 * 100) -#define SMBUS_SLAVE_ADDR 0x24 - -int do_smbus_read_byte(unsigned int smbus_base, unsigned int device, - unsigned int address); -int do_smbus_write_byte(unsigned int smbus_base, unsigned int device, - unsigned int address, unsigned int data); - -#endif diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h deleted file mode 100644 index 867bf60a5e..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BROADWELL_SMM_H_ -#define _BROADWELL_SMM_H_ - -#include <stdint.h> -#include <cpu/x86/msr.h> - - -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - msr_t prmrr_base; - msr_t prmrr_mask; - /* The smm_save_state_in_msrs field indicates if SMM save state - locations live in MSRs. This indicates to the CPUs how to adjust - the SMMBASE and IEDBASE. */ - int smm_save_state_in_msrs; -}; - - -#endif diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/ubox.h b/src/soc/intel/fsp_broadwell_de/include/soc/ubox.h deleted file mode 100644 index 3c2e6f50a6..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/ubox.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Facebook, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * As per "Intel Xeon Processor D-1500 Product Family" volume 2, - * "The UBOX [Processor Utility Box] is the piece of processor logic that deals with - * the non mainstream flows in the system. This includes transactions like the register - * accesses, interrupt flows, lock flows and events. In addition, the UBOX houses - * coordination for the performance architecture, and also houses scratchpad and - * semaphore registers." - * - * In other words, this is a one-die block that has all the useful magic registers. -*/ - -#ifndef _BROADWELL_UBOX_H_ -#define _BROADWELL_UBOX_H_ - -#include <device/pci_ops.h> -#include <soc/pci_devs.h> -#include <soc/vtd.h> - -#define UBOX_UART_ENABLE 0xf8 -#define UBOX_UART_ENABLE_PORT0 (1u << 0) -#define UBOX_UART_ENABLE_PORT1 (1u << 1) - -#define UBOX_SC_RESET_STATUS 0xc8 -#define UBOX_SC_BYPASS (1u << 3) - -#define UBOX_DEVHIDE0 0xb0 - -void iio_hide(DEVTREE_CONST struct device *dev); -#endif diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/vtd.h b/src/soc/intel/fsp_broadwell_de/include/soc/vtd.h deleted file mode 100644 index f1087d1997..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/vtd.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Facebook, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BROADWELL_VTD_H_ -#define _BROADWELL_VTD_H_ - -#include <device/pci_ops.h> -#include <soc/pci_devs.h> - -#define VTD_CPUBUSNO 0x108 -#define VTD_CPUBUSNO_BUS0_MASK 0xff -#define VTD_CPUBUSNO_BUS0_SHIFT 0 -#define VTD_CPUBUSNO_BUS1_MASK 0xff -#define VTD_CPUBUSNO_BUS1_SHIFT 8 -#define VTD_CPUBUSNO_ISVALID (1u << 16) - -#define VTD_DFX1 0x804 -#define VTD_DFX1_RANGE_3F8_DISABLE (1u << 29) -#define VTD_DFX1_RANGE_2F8_DISABLE (1u << 30) - -uint8_t get_busno1(void); - -#endif |