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-rw-r--r--src/soc/intel/fsp_broadwell_de/fsp/Kconfig140
1 files changed, 0 insertions, 140 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/fsp/Kconfig b/src/soc/intel/fsp_broadwell_de/fsp/Kconfig
deleted file mode 100644
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--- a/src/soc/intel/fsp_broadwell_de/fsp/Kconfig
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@@ -1,140 +0,0 @@
-config BROADWELL_DE_FSP_SPECIFIC_OPTIONS
- def_bool y
- select PLATFORM_USES_FSP1_0
- select USE_GENERIC_FSP_CAR_INC
- select FSP_USES_UPD
-
-config FSP_FILE
- string
- default "3rdparty/fsp/BroadwellDEFspBinPkg/FspBin/BROADWELLDE_FSP.bin"
- help
- The path and filename of the Intel FSP binary for this platform.
-
-config FSP_HEADER_PATH
- string
- default "$(top)/3rdparty/fsp/BroadwellDEFspBinPkg/include/"
-
-config FSP_SRC_PATH
- string
- default "$(top)/3rdparty/fsp/BroadwellDEFspBinPkg/include/fspsupport.c"
-
-config FSP_LOC
- hex
- default 0xffeb0000
- help
- The location in CBFS that the FSP is located. This must match the
- value that is set in the FSP binary. If the FSP needs to be moved,
- rebase the FSP with Intel's BCT (tool).
-
- The Broadwell-DE FSP is built with a preferred base address of
- 0xffeb0000.
-
-config DCACHE_RAM_BASE
- hex
- default 0xfe100000
- help
- This address needs to match the setup performed inside FSP.
- On Broadwell-DE the FSP allocates temporary RAM starting at 0xfe100000.
-
-config DCACHE_RAM_SIZE
- hex
- default 0x8000
- help
- The DCACHE is shared between FSP itself and the rest of the coreboot
- stages. A size of 0x8000 works fine while providing enough space for
- features like VBOOT in verstage. Further increase to a power of two
- aligned value leads to errors in FSP.
-
-config FSP_MEMORY_DOWN
- bool "Enable Memory Down"
- default n
- help
- Load SPD data from ROM instead of trying to read from SMBus.
-
- If the platform has DIMM sockets, say N. If memory is down, say Y and
- supply the appropriate SPD data for each Channel/DIMM.
-
-config FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT
- bool "Channel 0, DIMM 0 Present"
- default n
- depends on FSP_MEMORY_DOWN
- help
- Select Y if Channel 0, DIMM 0 is present.
-
-config FSP_MEMORY_DOWN_CH0DIMM0_SPD_FILE
- string "Channel 0, DIMM 0 SPD File"
- default "spd_ch0_dimm0.bin"
- depends on FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT
- help
- Path to the file which contains the SPD data for Channel 0, DIMM 0.
-
-config FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT
- bool "Channel 0, DIMM 1 Present"
- default n
- depends on FSP_MEMORY_DOWN
- help
- Select Y if Channel 0, DIMM 1 is present.
-
-config FSP_MEMORY_DOWN_CH0DIMM1_SPD_FILE
- string "Channel 0, DIMM 1 SPD File"
- default "spd_ch0_dimm1.bin"
- depends on FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT
- help
- Path to the file which contains the SPD data for Channel 0, DIMM 1.
-
-config FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT
- bool "Channel 1, DIMM 0 Present"
- default n
- depends on FSP_MEMORY_DOWN
- help
- Select Y if Channel 1, DIMM 0 is present.
-
-config FSP_MEMORY_DOWN_CH1DIMM0_SPD_FILE
- string "Channel 1, DIMM 0 SPD File"
- default "spd_ch1_dimm0.bin"
- depends on FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT
- help
- Path to the file which contains the SPD data for Channel 1, DIMM 0.
-
-config FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT
- bool "Channel 1, DIMM 1 Present"
- default n
- depends on FSP_MEMORY_DOWN
- help
- Select Y if Channel 1, DIMM 1 is present.
-
-config FSP_MEMORY_DOWN_CH1DIMM1_SPD_FILE
- string "Channel 1, DIMM 1 SPD File"
- default "spd_ch1_dimm1.bin"
- depends on FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT
- help
- Path to the file which contains the SPD data for Channel 1, DIMM 1.
-
-config FSP_HYPERTHREADING
- bool "Enable Hyper-Threading"
- default y
- help
- Enable Intel(r) Hyper-Threading Technology for the Broadwell-DE SoC.
-
-config FSP_EHCI1_ENABLE
- bool "EHCI1 Enable"
- default n
- help
- Enable EHCI controller 1
-
-config FSP_EHCI2_ENABLE
- bool "EHCI2 Enable"
- default n
- help
- Enable EHCI controller 2
-
-config FSP_DEBUG_LEVEL
- int "FSP debug level (0-3)"
- default 0
- range 0 3
- help
- Select the debug level, where:
- 0: DISABLED
- 1: MINIMUM
- 2: NORMAL
- 3: MAXIMUM