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Diffstat (limited to 'src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h')
-rwxr-xr-x[-rw-r--r--]src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h
index 1b603986ea..6df14845d8 100644..100755
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2014 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -46,4 +47,7 @@
#define FSP_IMAGE_ID_DWORD0 0x56594C56 /* 'VLYV' */
#define FSP_IMAGE_ID_DWORD1 0x30574549 /* 'IEW0' */
+/* Revision of the FSP binary */
+#define FSP_GOLD3_REV_ID 0x00000303
+
#endif /* CHIPSET_FSP_UTIL_H */