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-rw-r--r--src/soc/intel/elkhartlake/include/soc/cpu.h33
-rw-r--r--src/soc/intel/elkhartlake/include/soc/espi.h8
-rw-r--r--src/soc/intel/elkhartlake/include/soc/gpe.h121
-rw-r--r--src/soc/intel/elkhartlake/include/soc/gpio.h15
-rw-r--r--src/soc/intel/elkhartlake/include/soc/gpio_defs.h260
-rw-r--r--src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h347
-rw-r--r--src/soc/intel/elkhartlake/include/soc/irq.h36
-rw-r--r--src/soc/intel/elkhartlake/include/soc/itss.h13
-rw-r--r--src/soc/intel/elkhartlake/include/soc/me.h123
-rw-r--r--src/soc/intel/elkhartlake/include/soc/meminit.h112
-rw-r--r--src/soc/intel/elkhartlake/include/soc/msr.h11
-rw-r--r--src/soc/intel/elkhartlake/include/soc/nvs.h8
-rw-r--r--src/soc/intel/elkhartlake/include/soc/pmc.h138
-rw-r--r--src/soc/intel/elkhartlake/include/soc/ramstage.h14
-rw-r--r--src/soc/intel/elkhartlake/include/soc/serialio.h36
-rw-r--r--src/soc/intel/elkhartlake/include/soc/usb.h139
16 files changed, 1411 insertions, 3 deletions
diff --git a/src/soc/intel/elkhartlake/include/soc/cpu.h b/src/soc/intel/elkhartlake/include/soc/cpu.h
new file mode 100644
index 0000000000..6ee34f234c
--- /dev/null
+++ b/src/soc/intel/elkhartlake/include/soc/cpu.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_ELKHARTLAKE_CPU_H_
+#define _SOC_ELKHARTLAKE_CPU_H_
+
+#include <intelblocks/msr.h>
+
+/* Latency times in us */
+#define C1_LATENCY 1
+#define C6_LATENCY 127
+#define C7_LATENCY 253
+#define C8_LATENCY 260
+#define C9_LATENCY 487
+#define C10_LATENCY 1048
+
+/* Power in units of mW */
+#define C1_POWER 0x3e8
+#define C6_POWER 0x15e
+#define C7_POWER 0xc8
+#define C8_POWER 0xc8
+#define C9_POWER 0xc8
+#define C10_POWER 0xc8
+
+/* Common Timer Copy (CTC) frequency - 38.4MHz. */
+#define CTC_FREQ 38400000
+
+#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
+ (((1 << ((base)*5)) * (limit)) / 1000)
+#define C_STATE_LATENCY_FROM_LAT_REG(reg) \
+ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
+ (IRTL_1024_NS >> 10))
+
+#endif
diff --git a/src/soc/intel/elkhartlake/include/soc/espi.h b/src/soc/intel/elkhartlake/include/soc/espi.h
index 80b5c1e49e..6c2615816e 100644
--- a/src/soc/intel/elkhartlake/include/soc/espi.h
+++ b/src/soc/intel/elkhartlake/include/soc/espi.h
@@ -15,14 +15,16 @@
#define SCIS_IRQ23 7
#define SERIRQ_CNTL 0x64
#define ESPI_IO_DEC 0x80 /* IO Decode Ranges Register */
-#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/
-#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/
+#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/
+#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/
#define ESPI_GEN1_DEC 0x84 /* ESPI IF Generic Decode Range 1 */
#define ESPI_GEN2_DEC 0x88 /* ESPI IF Generic Decode Range 2 */
#define ESPI_GEN3_DEC 0x8c /* ESPI IF Generic Decode Range 3 */
#define ESPI_GEN4_DEC 0x90 /* ESPI IF Generic Decode Range 4 */
#define LGMR 0x98 /* ESPI Generic Memory Range */
+#define NMI_EN 0x70
+#define NMI_STS_CNT 0x61
#define PCCTL 0xE0 /* PCI Clock Control */
-#define CLKRUN_EN (1 << 0)
+#define CLKRUN_EN (1 << 0)
#endif
diff --git a/src/soc/intel/elkhartlake/include/soc/gpe.h b/src/soc/intel/elkhartlake/include/soc/gpe.h
new file mode 100644
index 0000000000..34dfcea763
--- /dev/null
+++ b/src/soc/intel/elkhartlake/include/soc/gpe.h
@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_GPE_H_
+#define _SOC_GPE_H_
+
+/* GPE_31_0 */
+#define GPE0_DW0_00 0
+#define GPE0_DW0_01 1
+#define GPE0_DW0_02 2
+#define GPE0_DW0_03 3
+#define GPE0_DW0_04 4
+#define GPE0_DW0_05 5
+#define GPE0_DW0_06 6
+#define GPE0_DW0_07 7
+#define GPE0_DW0_08 8
+#define GPE0_DW0_09 9
+#define GPE0_DW0_10 10
+#define GPE0_DW0_11 11
+#define GPE0_DW0_12 12
+#define GPE0_DW0_13 13
+#define GPE0_DW0_14 14
+#define GPE0_DW0_15 15
+#define GPE0_DW0_16 16
+#define GPE0_DW0_17 17
+#define GPE0_DW0_18 18
+#define GPE0_DW0_19 19
+#define GPE0_DW0_20 20
+#define GPE0_DW0_21 21
+#define GPE0_DW0_22 22
+#define GPE0_DW0_23 23
+#define GPE0_DW0_24 24
+#define GPE0_DW0_25 25
+#define GPE0_DW0_26 26
+#define GPE0_DW0_27 27
+#define GPE0_DW0_28 28
+#define GPE0_DW0_29 29
+#define GPE0_DW0_30 30
+#define GPE0_DW0_31 31
+/* GPE_63_32 */
+#define GPE0_DW1_00 32
+#define GPE0_DW1_01 33
+#define GPE0_DW1_02 34
+#define GPE0_DW1_03 36
+#define GPE0_DW1_04 36
+#define GPE0_DW1_05 37
+#define GPE0_DW1_06 38
+#define GPE0_DW1_07 39
+#define GPE0_DW1_08 40
+#define GPE0_DW1_09 41
+#define GPE0_DW1_10 42
+#define GPE0_DW1_11 43
+#define GPE0_DW1_12 44
+#define GPE0_DW1_13 45
+#define GPE0_DW1_14 46
+#define GPE0_DW1_15 47
+#define GPE0_DW1_16 48
+#define GPE0_DW1_17 49
+#define GPE0_DW1_18 50
+#define GPE0_DW1_19 51
+#define GPE0_DW1_20 52
+#define GPE0_DW1_21 53
+#define GPE0_DW1_22 54
+#define GPE0_DW1_23 55
+#define GPE0_DW1_24 56
+#define GPE0_DW1_25 57
+#define GPE0_DW1_26 58
+#define GPE0_DW1_27 59
+#define GPE0_DW1_28 60
+#define GPE0_DW1_29 61
+#define GPE0_DW1_30 62
+#define GPE0_DW1_31 63
+/* GPE_95_64 */
+#define GPE0_DW2_00 64
+#define GPE0_DW2_01 65
+#define GPE0_DW2_02 66
+#define GPE0_DW2_03 67
+#define GPE0_DW2_04 68
+#define GPE0_DW2_05 69
+#define GPE0_DW2_06 70
+#define GPE0_DW2_07 71
+#define GPE0_DW2_08 72
+#define GPE0_DW2_09 73
+#define GPE0_DW2_10 74
+#define GPE0_DW2_11 75
+#define GPE0_DW2_12 76
+#define GPE0_DW2_13 77
+#define GPE0_DW2_14 78
+#define GPE0_DW2_15 79
+#define GPE0_DW2_16 80
+#define GPE0_DW2_17 81
+#define GPE0_DW2_18 82
+#define GPE0_DW2_19 83
+#define GPE0_DW2_20 84
+#define GPE0_DW2_21 85
+#define GPE0_DW2_22 86
+#define GPE0_DW2_23 87
+#define GPE0_DW2_24 88
+#define GPE0_DW2_25 89
+#define GPE0_DW2_26 90
+#define GPE0_DW2_27 91
+#define GPE0_DW2_28 92
+#define GPE0_DW2_29 93
+#define GPE0_DW2_30 94
+#define GPE0_DW2_31 95
+/* GPE_STD */
+#define GPE0_HOT_PLUG 97
+#define GPE0_SWGPE 98
+#define GPE0_TCOSCI 102
+#define GPE0_SMB_WAK 103
+#define GPE0_PCI_EXP 105
+#define GPE0_BATLOW 106
+#define GPE0_PME 107
+#define GPE0_ME_SCI 108
+#define GPE0_PME_B0 109
+#define GPE0_ESPI 110
+#define GPE0_GPIO_T2 111
+#define GPE0_LAN_WAK 112
+#define GPE0_WADT 114
+
+#define GPE_MAX GPE0_WADT
+#endif /* _SOC_GPE_H_ */
diff --git a/src/soc/intel/elkhartlake/include/soc/gpio.h b/src/soc/intel/elkhartlake/include/soc/gpio.h
new file mode 100644
index 0000000000..6cca742614
--- /dev/null
+++ b/src/soc/intel/elkhartlake/include/soc/gpio.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_ELKHARTLAKE_GPIO_H_
+#define _SOC_ELKHARTLAKE_GPIO_H_
+
+#include <intelblocks/gpio.h>
+#include <soc/gpio_defs.h>
+
+#define CROS_GPIO_NAME "INT34C8"
+#define CROS_GPIO_COMM0_NAME "INT34C8:00"
+#define CROS_GPIO_COMM1_NAME "INT34C8:01"
+#define CROS_GPIO_COMM4_NAME "INT34C8:02"
+#define CROS_GPIO_COMM5_NAME "INT34C8:03"
+
+#endif
diff --git a/src/soc/intel/elkhartlake/include/soc/gpio_defs.h b/src/soc/intel/elkhartlake/include/soc/gpio_defs.h
new file mode 100644
index 0000000000..0b8d8a74a9
--- /dev/null
+++ b/src/soc/intel/elkhartlake/include/soc/gpio_defs.h
@@ -0,0 +1,260 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_ELKHARTLAKE_GPIO_DEFS_H_
+#define _SOC_ELKHARTLAKE_GPIO_DEFS_H_
+
+#ifndef __ACPI__
+#include <stddef.h>
+#endif
+#include <soc/gpio_soc_defs.h>
+
+
+#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */
+
+#define NUM_GPIO_COMx_GPI_REGS(n) \
+ (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)
+#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)
+#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)
+#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS)
+#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS)
+
+#define NUM_GPI_STATUS_REGS \
+ ((NUM_GPIO_COM0_GPI_REGS) +\
+ (NUM_GPIO_COM1_GPI_REGS) +\
+ (NUM_GPIO_COM2_GPI_REGS) +\
+ (NUM_GPIO_COM4_GPI_REGS) +\
+ (NUM_GPIO_COM5_GPI_REGS))
+/*
+ * IOxAPIC IRQs for the GPIOs
+ */
+
+/* Group F */
+#define GPP_F0_IRQ 0x40
+#define GPP_F1_IRQ 0x41
+#define GPP_F2_IRQ 0x42
+#define GPP_F3_IRQ 0x43
+#define GPP_F4_IRQ 0x44
+#define GPP_F5_IRQ 0x45
+#define GPP_F6_IRQ 0x46
+#define GPP_F7_IRQ 0x47
+#define GPP_F8_IRQ 0x48
+#define GPP_F9_IRQ 0x49
+#define GPP_F10_IRQ 0x4a
+#define GPP_F11_IRQ 0x4b
+#define GPP_F12_IRQ 0x4c
+#define GPP_F13_IRQ 0x4d
+#define GPP_F14_IRQ 0x4e
+#define GPP_F15_IRQ 0x4f
+#define GPP_F16_IRQ 0x50
+#define GPP_F17_IRQ 0x51
+#define GPP_F18_IRQ 0x52
+#define GPP_F19_IRQ 0x53
+
+/* Group G */
+#define GPP_G0_IRQ 0x18
+#define GPP_G1_IRQ 0x19
+#define GPP_G2_IRQ 0x1a
+#define GPP_G3_IRQ 0x1b
+#define GPP_G4_IRQ 0x1c
+#define GPP_G5_IRQ 0x1d
+#define GPP_G6_IRQ 0x1e
+#define GPP_G7_IRQ 0x1f
+
+/* Group B */
+#define GPP_B0_IRQ 0x20
+#define GPP_B1_IRQ 0x21
+#define GPP_B2_IRQ 0x22
+#define GPP_B3_IRQ 0x23
+#define GPP_B4_IRQ 0x24
+#define GPP_B5_IRQ 0x25
+#define GPP_B6_IRQ 0x26
+#define GPP_B7_IRQ 0x27
+#define GPP_B8_IRQ 0x28
+#define GPP_B9_IRQ 0x29
+#define GPP_B10_IRQ 0x2a
+#define GPP_B11_IRQ 0x2b
+#define GPP_B12_IRQ 0x2c
+#define GPP_B13_IRQ 0x2d
+#define GPP_B14_IRQ 0x2e
+#define GPP_B15_IRQ 0x2f
+#define GPP_B16_IRQ 0x30
+#define GPP_B17_IRQ 0x31
+#define GPP_B18_IRQ 0x32
+#define GPP_B19_IRQ 0x33
+#define GPP_B20_IRQ 0x34
+#define GPP_B21_IRQ 0x35
+#define GPP_B22_IRQ 0x36
+#define GPP_B23_IRQ 0x37
+
+/* Group A */
+#define GPP_A0_IRQ 0x38
+#define GPP_A1_IRQ 0x39
+#define GPP_A2_IRQ 0x3a
+#define GPP_A3_IRQ 0x3b
+#define GPP_A4_IRQ 0x3c
+#define GPP_A5_IRQ 0x3d
+#define GPP_A6_IRQ 0x3e
+#define GPP_A7_IRQ 0x3f
+#define GPP_A8_IRQ 0x40
+#define GPP_A9_IRQ 0x41
+#define GPP_A10_IRQ 0x42
+#define GPP_A11_IRQ 0x43
+#define GPP_A12_IRQ 0x44
+#define GPP_A13_IRQ 0x45
+#define GPP_A14_IRQ 0x46
+#define GPP_A15_IRQ 0x47
+#define GPP_A16_IRQ 0x48
+#define GPP_A17_IRQ 0x49
+#define GPP_A18_IRQ 0x4a
+#define GPP_A19_IRQ 0x4b
+
+/* Group H */
+#define GPP_H0_IRQ 0x70
+#define GPP_H1_IRQ 0x71
+#define GPP_H2_IRQ 0x72
+#define GPP_H3_IRQ 0x73
+#define GPP_H4_IRQ 0x74
+#define GPP_H5_IRQ 0x75
+#define GPP_H6_IRQ 0x76
+#define GPP_H7_IRQ 0x77
+#define GPP_H8_IRQ 0x18
+#define GPP_H9_IRQ 0x19
+#define GPP_H10_IRQ 0x1a
+#define GPP_H11_IRQ 0x1b
+#define GPP_H12_IRQ 0x1c
+#define GPP_H13_IRQ 0x1d
+#define GPP_H14_IRQ 0x1e
+#define GPP_H15_IRQ 0x1f
+#define GPP_H16_IRQ 0x20
+#define GPP_H17_IRQ 0x21
+#define GPP_H18_IRQ 0x22
+#define GPP_H19_IRQ 0x23
+#define GPP_H20_IRQ 0x24
+#define GPP_H21_IRQ 0x25
+#define GPP_H22_IRQ 0x26
+#define GPP_H23_IRQ 0x27
+
+/* Group D */
+#define GPP_D0_IRQ 0x28
+#define GPP_D1_IRQ 0x29
+#define GPP_D2_IRQ 0x2a
+#define GPP_D3_IRQ 0x2b
+#define GPP_D4_IRQ 0x2c
+#define GPP_D5_IRQ 0x2d
+#define GPP_D6_IRQ 0x2e
+#define GPP_D7_IRQ 0x2f
+#define GPP_D8_IRQ 0x30
+#define GPP_D9_IRQ 0x31
+#define GPP_D10_IRQ 0x32
+#define GPP_D11_IRQ 0x33
+#define GPP_D12_IRQ 0x34
+#define GPP_D13_IRQ 0x35
+#define GPP_D14_IRQ 0x36
+#define GPP_D15_IRQ 0x37
+#define GPP_D16_IRQ 0x38
+#define GPP_D17_IRQ 0x39
+#define GPP_D18_IRQ 0x3a
+#define GPP_D19_IRQ 0x3b
+#define GPP_D20_IRQ 0x3c
+#define GPP_D21_IRQ 0x3d
+#define GPP_D22_IRQ 0x3e
+#define GPP_D23_IRQ 0x3f
+
+/* Group GPD */
+#define GPD0_IRQ 0x64
+#define GPD1_IRQ 0x65
+#define GPD2_IRQ 0x66
+#define GPD3_IRQ 0x67
+#define GPD4_IRQ 0x68
+#define GPD5_IRQ 0x69
+#define GPD6_IRQ 0x6a
+#define GPD7_IRQ 0x6b
+#define GPD8_IRQ 0x6c
+#define GPD9_IRQ 0x6d
+#define GPD10_IRQ 0x6e
+
+/* Group C */
+#define GPP_C0_IRQ 0x5a
+#define GPP_C1_IRQ 0x5b
+#define GPP_C2_IRQ 0x5c
+#define GPP_C3_IRQ 0x5d
+#define GPP_C4_IRQ 0x5e
+#define GPP_C5_IRQ 0x5f
+#define GPP_C6_IRQ 0x60
+#define GPP_C7_IRQ 0x61
+#define GPP_C8_IRQ 0x62
+#define GPP_C9_IRQ 0x63
+#define GPP_C10_IRQ 0x64
+#define GPP_C11_IRQ 0x65
+#define GPP_C12_IRQ 0x66
+#define GPP_C13_IRQ 0x67
+#define GPP_C14_IRQ 0x68
+#define GPP_C15_IRQ 0x69
+#define GPP_C16_IRQ 0x6a
+#define GPP_C17_IRQ 0x6b
+#define GPP_C18_IRQ 0x6c
+#define GPP_C19_IRQ 0x6d
+#define GPP_C20_IRQ 0x6e
+#define GPP_C21_IRQ 0x6f
+#define GPP_C22_IRQ 0x70
+#define GPP_C23_IRQ 0x71
+/* Group E */
+#define GPP_E0_IRQ 0x72
+#define GPP_E1_IRQ 0x73
+#define GPP_E2_IRQ 0x74
+#define GPP_E3_IRQ 0x75
+#define GPP_E4_IRQ 0x76
+#define GPP_E5_IRQ 0x77
+#define GPP_E6_IRQ 0x18
+#define GPP_E7_IRQ 0x19
+#define GPP_E8_IRQ 0x1a
+#define GPP_E9_IRQ 0x1b
+#define GPP_E10_IRQ 0x1c
+#define GPP_E11_IRQ 0x1d
+#define GPP_E12_IRQ 0x1e
+#define GPP_E13_IRQ 0x1f
+#define GPP_E14_IRQ 0x20
+#define GPP_E15_IRQ 0x21
+#define GPP_E16_IRQ 0x22
+#define GPP_E17_IRQ 0x23
+#define GPP_E18_IRQ 0x24
+#define GPP_E19_IRQ 0x25
+#define GPP_E20_IRQ 0x26
+#define GPP_E21_IRQ 0x27
+#define GPP_E22_IRQ 0x28
+#define GPP_E23_IRQ 0x29
+
+/* Group R*/
+#define GPP_R0_IRQ 0x50
+#define GPP_R1_IRQ 0x51
+#define GPP_R2_IRQ 0x52
+#define GPP_R3_IRQ 0x53
+#define GPP_R4_IRQ 0x54
+#define GPP_R5_IRQ 0x55
+#define GPP_R6_IRQ 0x56
+#define GPP_R7_IRQ 0x57
+
+/* Group S */
+#define GPP_S0_IRQ 0x5c
+#define GPP_S1_IRQ 0x5d
+#define GPP_S2_IRQ 0x5e
+#define GPP_S3_IRQ 0x5f
+#define GPP_S4_IRQ 0x60
+#define GPP_S5_IRQ 0x61
+#define GPP_S6_IRQ 0x62
+#define GPP_S7_IRQ 0x63
+
+/* Register defines. */
+#define GPIO_MISCCFG 0x10
+#define GPE_DW_SHIFT 8
+#define GPE_DW_MASK 0xfff00
+#define HOSTSW_OWN_REG_0 0xc0
+#define GPI_INT_STS_0 0x100
+#define GPI_INT_EN_0 0x120
+#define GPI_SMI_STS_0 0x180
+#define GPI_SMI_EN_0 0x1a0
+#define PAD_CFG_BASE 0x600
+
+#endif
diff --git a/src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h b/src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h
new file mode 100644
index 0000000000..278c2c63aa
--- /dev/null
+++ b/src/soc/intel/elkhartlake/include/soc/gpio_soc_defs.h
@@ -0,0 +1,347 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_ELKHARTLAKE_GPIO_SOC_DEFS_H_
+#define _SOC_ELKHARTLAKE_GPIO_SOC_DEFS_H_
+
+/*
+ * Most of the fixed numbers and macros are based on the GPP groups.
+ * The GPIO groups are accessed through register blocks called
+ * communities.
+ */
+
+#define GPP_A 0x0
+#define GPP_B 0x1
+#define GPP_G 0x2
+#define GPP_C 0x3
+#define GPP_R 0x4
+#define GPP_D 0x5
+#define GPP_S 0x6
+#define GPP_H 0x7
+#define GPP_VGPIO 0x8
+#define GPP_F 0x9
+#define GPP_GPD 0xA
+#define GPP_E 0xD
+
+#define GPIO_NUM_GROUPS 12
+#define GPIO_MAX_NUM_PER_GROUP 24
+#define SD_PWR_EN_PIN GPP_H1
+
+/*
+ * GPIOs are ordered monotonically increasing to match ACPI/OS driver.
+ */
+
+/* Group F */
+#define GPP_F0 0
+#define GPP_F1 1
+#define GPP_F2 2
+#define GPP_F3 3
+#define GPP_F4 4
+#define GPP_F5 5
+#define GPP_F6 6
+#define GPP_F7 7
+#define GPP_F8 8
+#define GPP_F9 9
+#define GPP_F10 10
+#define GPP_F11 11
+#define GPP_F12 12
+#define GPP_F13 13
+#define GPP_F14 14
+#define GPP_F15 15
+#define GPP_F16 16
+#define GPP_F17 17
+#define GPP_F18 18
+#define GPP_F19 19
+
+/* Group B */
+#define GPIO_RSVD_0 20
+#define GPIO_RSVD_1 21
+#define GPIO_RSVD_2 22
+#define GPIO_RSVD_3 23
+#define GPIO_RSVD_4 24
+#define GPIO_RSVD_5 25
+#define GPIO_RSVD_6 26
+#define GPIO_RSVD_7 27
+#define GPIO_RSVD_8 28
+#define GPP_B0 29
+#define GPP_B1 30
+#define GPP_B2 31
+#define GPP_B3 32
+#define GPP_B4 33
+#define GPP_B5 34
+#define GPP_B6 35
+#define GPP_B7 36
+#define GPP_B8 37
+#define GPP_B9 38
+#define GPP_B10 39
+#define GPP_B11 40
+#define GPP_B12 41
+#define GPP_B13 42
+#define GPP_B14 43
+#define GPP_B15 44
+#define GPP_B16 45
+#define GPP_B17 46
+#define GPP_B18 47
+#define GPP_B19 48
+#define GPP_B20 49
+#define GPP_B21 50
+#define GPP_B22 51
+#define GPP_B23 52
+#define GPIO_RSVD_9 53
+#define GPIO_RSVD_10 54
+
+/* Group A */
+#define GPP_A0 55
+#define GPP_A1 56
+#define GPP_A2 57
+#define GPP_A3 58
+#define GPP_A4 59
+#define GPP_A5 60
+#define GPP_A6 61
+#define GPP_A7 62
+#define GPP_A8 63
+#define GPP_A9 64
+#define GPP_A10 65
+#define GPP_A11 66
+#define GPP_A12 67
+#define GPP_A13 68
+#define GPP_A14 69
+#define GPP_A15 70
+#define GPP_A16 71
+#define GPP_A17 72
+#define GPP_A18 73
+#define GPP_A19 74
+#define GPIO_RSVD_11 75
+
+/* Group S */
+#define GPP_S0 76
+#define GPP_S1 77
+#define GPP_S2 78
+#define GPP_S3 79
+#define GPP_S4 80
+#define GPP_S5 81
+#define GPP_S6 82
+#define GPP_S7 83
+
+/* Group R */
+#define GPP_R0 84
+#define GPP_R1 85
+#define GPP_R2 86
+#define GPP_R3 87
+#define GPP_R4 88
+#define GPP_R5 89
+#define GPP_R6 90
+#define GPP_R7 91
+
+#define GPIO_COM0_START GPP_F0
+#define GPIO_COM0_END GPP_R7
+#define NUM_GPIO_COM0_PADS (GPIO_COM0_END - GPIO_COM0_START + 1)
+
+/* Group H */
+#define GPP_H0 92
+#define GPP_H1 93
+#define GPP_H2 94
+#define GPP_H3 95
+#define GPP_H4 96
+#define GPP_H5 97
+#define GPP_H6 98
+#define GPP_H7 99
+#define GPP_H8 100
+#define GPP_H9 101
+#define GPP_H10 102
+#define GPP_H11 103
+#define GPP_H12 104
+#define GPP_H13 105
+#define GPP_H14 106
+#define GPP_H15 107
+#define GPP_H16 108
+#define GPP_H17 109
+#define GPP_H18 110
+#define GPP_H19 111
+#define GPP_H20 112
+#define GPP_H21 113
+#define GPP_H22 114
+#define GPP_H23 115
+
+/* Group D */
+#define GPP_D0 116
+#define GPP_D1 117
+#define GPP_D2 118
+#define GPP_D3 119
+#define GPP_D4 120
+#define GPP_D5 121
+#define GPP_D6 122
+#define GPP_D7 123
+#define GPP_D8 124
+#define GPP_D9 125
+#define GPP_D10 126
+#define GPP_D11 127
+#define GPP_D12 128
+#define GPP_D13 129
+#define GPP_D14 130
+#define GPP_D15 131
+#define GPP_D16 132
+#define GPP_D17 133
+#define GPP_D18 134
+#define GPP_D19 135
+#define GPP_D20 136
+#define GPP_D21 137
+#define GPP_D22 138
+#define GPP_D23 139
+#define GPIO_RSVD_12 140
+#define GPIO_RSVD_13 141
+
+/* Group VGPIO */
+#define VGPIO_0 142
+#define VGPIO_3 143
+#define VGPIO_4 144
+#define VGPIO_5 145
+#define VGPIO_6 146
+#define VGPIO_7 147
+#define VGPIO_8 148
+#define VGPIO_9 149
+#define VGPIO_10 150
+#define VGPIO_11 151
+#define VGPIO_12 152
+#define VGPIO_13 153
+#define VGPIO_18 154
+#define VGPIO_19 155
+#define VGPIO_20 156
+#define VGPIO_21 157
+#define VGPIO_22 158
+#define VGPIO_23 159
+#define VGPIO_24 160
+#define VGPIO_25 161
+#define VGPIO_30 162
+#define VGPIO_31 163
+#define VGPIO_32 164
+#define VGPIO_33 165
+#define VGPIO_34 166
+#define VGPIO_35 167
+#define VGPIO_36 168
+#define VGPIO_37 169
+#define VGPIO_39 170
+
+/* Group C */
+#define GPP_C0 171
+#define GPP_C1 172
+#define GPP_C2 173
+#define GPP_C3 174
+#define GPP_C4 175
+#define GPP_C5 176
+#define GPP_C6 177
+#define GPP_C7 178
+#define GPP_C8 179
+#define GPP_C9 180
+#define GPP_C10 181
+#define GPP_C11 182
+#define GPP_C12 183
+#define GPP_C13 184
+#define GPP_C14 185
+#define GPP_C15 186
+#define GPP_C16 187
+#define GPP_C17 188
+#define GPP_C18 189
+#define GPP_C19 190
+#define GPP_C20 191
+#define GPP_C21 192
+#define GPP_C22 193
+#define GPP_C23 194
+
+#define GPIO_COM1_START GPP_H0
+#define GPIO_COM1_END GPP_C23
+#define NUM_GPIO_COM1_PADS (GPIO_COM1_END - GPIO_COM1_START + 1)
+
+/* Group GPD */
+#define GPD0 195
+#define GPD1 196
+#define GPD2 197
+#define GPD3 198
+#define GPD4 199
+#define GPD5 200
+#define GPD6 201
+#define GPD7 202
+#define GPD8 203
+#define GPD9 204
+#define GPD10 205
+#define GPIO_RSVD_14 206
+#define GPIO_RSVD_15 207
+#define GPIO_RSVD_16 208
+#define GPIO_RSVD_17 209
+
+#define GPIO_COM2_START GPD0
+#define GPIO_COM2_END GPIO_RSVD_17
+#define NUM_GPIO_COM2_PADS (GPIO_COM2_END - GPIO_COM2_START + 1)
+
+/* Group E */
+#define GPIO_RSVD_18 210
+#define GPIO_RSVD_19 211
+#define GPIO_RSVD_20 212
+#define GPIO_RSVD_21 213
+#define GPIO_RSVD_22 214
+#define GPIO_RSVD_23 215
+#define GPP_E0 216
+#define GPP_E1 217
+#define GPP_E2 218
+#define GPP_E3 219
+#define GPP_E4 220
+#define GPP_E5 221
+#define GPP_E6 222
+#define GPP_E7 223
+#define GPP_E8 224
+#define GPP_E9 225
+#define GPP_E10 226
+#define GPP_E11 227
+#define GPP_E12 228
+#define GPP_E13 229
+#define GPP_E14 230
+#define GPP_E15 231
+#define GPP_E16 232
+#define GPP_E17 233
+#define GPP_E18 234
+#define GPP_E19 235
+#define GPP_E20 236
+#define GPP_E21 237
+#define GPP_E22 238
+#define GPP_E23 239
+#define GPIO_RSVD_24 240
+#define GPIO_RSVD_25 241
+#define GPIO_RSVD_26 242
+#define GPIO_RSVD_27 243
+#define GPIO_RSVD_28 244
+#define GPIO_RSVD_29 245
+#define GPIO_RSVD_30 246
+#define GPIO_RSVD_31 247
+#define GPIO_RSVD_32 248
+#define GPIO_RSVD_33 249
+#define GPIO_RSVD_34 250
+#define GPIO_RSVD_35 251
+#define GPIO_RSVD_36 252
+
+#define GPIO_COM4_START GPIO_RSVD_18
+#define GPIO_COM4_END GPIO_RSVD_36
+#define NUM_GPIO_COM4_PADS (GPIO_COM4_END - GPIO_COM4_START + 1)
+
+/* Group G */
+#define GPP_G0 253
+#define GPP_G1 254
+#define GPP_G2 255
+#define GPP_G3 256
+#define GPP_G4 257
+#define GPP_G5 258
+#define GPP_G6 259
+#define GPP_G7 260
+
+#define GPIO_COM5_START GPP_G0
+#define GPIO_COM5_END GPP_G7
+#define NUM_GPIO_COM5_PADS (GPIO_COM5_END - GPIO_COM5_START + 1)
+
+#define TOTAL_PADS 261
+
+#define COMM_0 0
+#define COMM_1 1
+#define COMM_2 2
+#define COMM_4 3
+#define COMM_5 4
+#define TOTAL_GPIO_COMM 5
+
+#endif
diff --git a/src/soc/intel/elkhartlake/include/soc/irq.h b/src/soc/intel/elkhartlake/include/soc/irq.h
new file mode 100644
index 0000000000..ac45424476
--- /dev/null
+++ b/src/soc/intel/elkhartlake/include/soc/irq.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_EHL_IRQ_H_
+#define _SOC_EHL_IRQ_H_
+
+#define GPIO_IRQ14 14
+#define GPIO_IRQ15 15
+
+#define PCH_IRQ10 10
+#define PCH_IRQ11 11
+
+/* LPSS Device IRQs */
+#define LPSS_I2C0_IRQ 16
+#define LPSS_I2C1_IRQ 17
+#define LPSS_I2C2_IRQ 18
+#define LPSS_I2C3_IRQ 19
+#define LPSS_I2C4_IRQ 32
+#define LPSS_I2C5_IRQ 33
+#define LPSS_SPI0_IRQ 22
+#define LPSS_SPI1_IRQ 23
+#define LPSS_SPI2_IRQ 24
+#define LPSS_UART0_IRQ 20
+#define LPSS_UART1_IRQ 21
+#define LPSS_UART2_IRQ 34
+
+/* PCI shared IRQs */
+#define PCH_IRQ_16 16
+#define PCH_IRQ_17 17
+#define PCH_IRQ_18 18
+#define PCH_IRQ_19 19
+#define PCH_IRQ_20 20
+#define PCH_IRQ_21 21
+#define PCH_IRQ_22 22
+#define PCH_IRQ_23 23
+
+#endif /* _EHL_IRQ_H_ */
diff --git a/src/soc/intel/elkhartlake/include/soc/itss.h b/src/soc/intel/elkhartlake/include/soc/itss.h
new file mode 100644
index 0000000000..a550f4c922
--- /dev/null
+++ b/src/soc/intel/elkhartlake/include/soc/itss.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_INTEL_EHL_ITSS_H
+#define SOC_INTEL_EHL_ITSS_H
+
+#define GPIO_IRQ_START 50
+#define GPIO_IRQ_END ITSS_MAX_IRQ
+
+#define ITSS_MAX_IRQ 119
+#define IRQS_PER_IPC 32
+#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
+
+#endif /* SOC_INTEL_EHL_ITSS_H */
diff --git a/src/soc/intel/elkhartlake/include/soc/me.h b/src/soc/intel/elkhartlake/include/soc/me.h
new file mode 100644
index 0000000000..d845629e4a
--- /dev/null
+++ b/src/soc/intel/elkhartlake/include/soc/me.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _ELKHARTLAKE_ME_H_
+#define _ELKHARTLAKE_ME_H_
+
+/* ME Host Firmware Status register 1 */
+union me_hfsts1 {
+ uint32_t data;
+ struct {
+ uint32_t working_state: 4;
+ uint32_t mfg_mode: 1;
+ uint32_t fpt_bad: 1;
+ uint32_t operation_state: 3;
+ uint32_t fw_init_complete: 1;
+ uint32_t ft_bup_ld_flr: 1;
+ uint32_t update_in_progress: 1;
+ uint32_t error_code: 4;
+ uint32_t operation_mode: 4;
+ uint32_t reset_count: 4;
+ uint32_t boot_options_present: 1;
+ uint32_t reserved1: 1;
+ uint32_t bist_test_state: 1;
+ uint32_t bist_reset_request: 1;
+ uint32_t current_power_source: 2;
+ uint32_t reserved: 1;
+ uint32_t d0i3_support_valid: 1;
+ } __packed fields;
+};
+
+/* Host Firmware Status Register 2 */
+union me_hfsts2 {
+ uint32_t data;
+ struct {
+ uint32_t nftp_load_failure : 1;
+ uint32_t icc_prog_status : 2;
+ uint32_t invoke_mebx : 1;
+ uint32_t cpu_replaced : 1;
+ uint32_t rsvd0 : 1;
+ uint32_t mfs_failure : 1;
+ uint32_t warm_reset_rqst : 1;
+ uint32_t cpu_replaced_valid : 1;
+ uint32_t low_power_state : 1;
+ uint32_t me_power_gate : 1;
+ uint32_t ipu_needed : 1;
+ uint32_t forced_safe_boot : 1;
+ uint32_t rsvd1 : 2;
+ uint32_t listener_change : 1;
+ uint32_t status_data : 8;
+ uint32_t current_pmevent : 4;
+ uint32_t phase : 4;
+ } __packed fields;
+};
+
+/* ME Host Firmware Status Register 3 */
+union me_hfsts3 {
+ uint32_t data;
+ struct {
+ uint32_t reserved_0: 4;
+ uint32_t fw_sku: 3;
+ uint32_t reserved: 25;
+ } __packed fields;
+};
+
+/* Host Firmware Status Register 4 */
+union me_hfsts4 {
+ uint32_t data;
+ struct {
+ uint32_t rsvd0 : 9;
+ uint32_t enforcement_flow : 1;
+ uint32_t sx_resume_type : 1;
+ uint32_t rsvd1 : 1;
+ uint32_t tpms_disconnected : 1;
+ uint32_t rvsd2 : 1;
+ uint32_t fwsts_valid : 1;
+ uint32_t boot_guard_self_test : 1;
+ uint32_t rsvd3 : 16;
+ } __packed fields;
+};
+
+/* Host Firmware Status Register 5 */
+union me_hfsts5 {
+ uint32_t data;
+ struct {
+ uint32_t acm_active : 1;
+ uint32_t valid : 1;
+ uint32_t result_code_source : 1;
+ uint32_t error_status_code : 5;
+ uint32_t acm_done_sts : 1;
+ uint32_t timeout_count : 7;
+ uint32_t scrtm_indicator : 1;
+ uint32_t inc_boot_guard_acm : 4;
+ uint32_t inc_key_manifest : 4;
+ uint32_t inc_boot_policy : 4;
+ uint32_t rsvd0 : 2;
+ uint32_t start_enforcement : 1;
+ } __packed fields;
+};
+
+/* Host Firmware Status Register 6 */
+union me_hfsts6 {
+ uint32_t data;
+ struct {
+ uint32_t force_boot_guard_acm : 1;
+ uint32_t cpu_debug_disable : 1;
+ uint32_t bsp_init_disable : 1;
+ uint32_t protect_bios_env : 1;
+ uint32_t rsvd0 : 2;
+ uint32_t error_enforce_policy : 2;
+ uint32_t measured_boot : 1;
+ uint32_t verified_boot : 1;
+ uint32_t boot_guard_acmsvn : 4;
+ uint32_t kmsvn : 4;
+ uint32_t bpmsvn : 4;
+ uint32_t key_manifest_id : 4;
+ uint32_t boot_policy_status : 1;
+ uint32_t error : 1;
+ uint32_t boot_guard_disable : 1;
+ uint32_t fpf_disable : 1;
+ uint32_t fpf_soc_lock : 1;
+ uint32_t txt_support : 1;
+ } __packed fields;
+};
+#endif /* _ELKHARTLAKE_ME_H_ */
diff --git a/src/soc/intel/elkhartlake/include/soc/meminit.h b/src/soc/intel/elkhartlake/include/soc/meminit.h
new file mode 100644
index 0000000000..ea4664a150
--- /dev/null
+++ b/src/soc/intel/elkhartlake/include/soc/meminit.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_ELKHARTLAKE_MEMINIT_H_
+#define _SOC_ELKHARTLAKE_MEMINIT_H_
+
+#include <fsp/soc_binding.h>
+#include <types.h>
+
+/* Number of dq bits controlled per dqs */
+#define DQ_BITS_PER_DQS 8
+
+/* Number of memory packages, where a "package" represents a 64-bit solution */
+#define DDR_NUM_PACKAGES 2
+
+/* Number of DQ byte mappings */
+#define DDR_NUM_BYTE_MAPPINGS 6
+
+/* Number of memory DIMM slots available on Elkhart Lake */
+#define NUM_DIMM_SLOT 4
+
+/* 64-bit Channel identification */
+enum {
+ DDR_CH0,
+ DDR_CH1,
+ DDR_NUM_CHANNELS
+};
+
+struct spd_by_pointer {
+ size_t spd_data_len;
+ uintptr_t spd_data_ptr;
+};
+
+enum mem_info_read_type {
+ READ_SPD_CBFS, /* Find SPD file in CBFS. */
+ READ_SMBUS, /* Read on-module SPD by SMBUS. */
+ READ_SPD_MEMPTR /* Find SPD data from pointer. */
+};
+
+struct spd_info {
+ enum mem_info_read_type read_type;
+ union spd_data_by {
+ /* To read on-module SPD when read_type is READ_SMBUS. */
+ uint8_t spd_smbus_address[NUM_DIMM_SLOT];
+
+ /* To identify SPD file when read_type is READ_SPD_CBFS. */
+ int spd_index;
+
+ /* To find SPD data when read_type is READ_SPD_MEMPTR. */
+ struct spd_by_pointer spd_data_ptr_info;
+ } spd_spec;
+};
+
+/* Board-specific memory dq mapping information */
+struct mb_cfg {
+
+ /*
+ * For each channel, there are 6 sets of DQ byte mappings,
+ * where each set has a package 0 and a package 1 value (package 0
+ * represents the first 64-bit lpddr4 chip combination, and package 1
+ * represents the second 64-bit lpddr4 chip combination).
+ * The first three sets are for CLK, CMD, and CTL.
+ * The fsp package actually expects 6 sets, even though the last 3 sets
+ * are not used in EHL.
+ * We let the meminit_dq_dqs_map routine take care of clearing the
+ * unused fields for the caller.
+ * Note that dq_map is only used by LPDDR; it does not need to be
+ * initialized for designs using DDR4.
+ */
+ uint8_t dq_map[DDR_NUM_CHANNELS][DDR_NUM_BYTE_MAPPINGS][DDR_NUM_PACKAGES];
+
+ /*
+ * DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a
+ * mapping of a dq bit on the CPU to the bit it's connected to on
+ * the memory part. The array index represents the dqs bit number
+ * on the memory part, and the values in the array represent which
+ * pin on the CPU that DRAM pin connects to.
+ * dqs_map is only used by LPDDR; same comments apply as for dq_map
+ * above.
+ */
+ uint8_t dqs_map[DDR_NUM_CHANNELS][DQ_BITS_PER_DQS];
+
+ /*
+ * Rcomp resistor values. These values represent the resistance in
+ * ohms of the three rcomp resistors attached to the DDR_COMP_0,
+ * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
+ */
+ uint16_t rcomp_resistor[3];
+
+ /*
+ * Rcomp target values. These will typically be the following
+ * values for Elkhart Lake : { 80, 40, 40, 40, 30 }
+ */
+ uint16_t rcomp_targets[5];
+
+ /*
+ * Early Command Training Enable/Disable Control
+ * 1 = enable, 0 = disable
+ */
+ uint8_t ect;
+
+ /* Board type */
+ uint8_t UserBd;
+};
+
+/*
+ * Initialize default memory configurations for Elkhart Lake.
+ */
+
+void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg,
+ const struct spd_info *spd_info, bool half_populated);
+
+#endif /* _SOC_ELKHARTLAKE_MEMINIT_H_ */
diff --git a/src/soc/intel/elkhartlake/include/soc/msr.h b/src/soc/intel/elkhartlake/include/soc/msr.h
new file mode 100644
index 0000000000..67e09dcf41
--- /dev/null
+++ b/src/soc/intel/elkhartlake/include/soc/msr.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_MSR_H_
+#define _SOC_MSR_H_
+
+#include <intelblocks/msr.h>
+
+#define MSR_PIC_MSG_CONTROL 0x2e
+#define MSR_VR_MISC_CONFIG2 0x636
+
+#endif
diff --git a/src/soc/intel/elkhartlake/include/soc/nvs.h b/src/soc/intel/elkhartlake/include/soc/nvs.h
new file mode 100644
index 0000000000..512945898e
--- /dev/null
+++ b/src/soc/intel/elkhartlake/include/soc/nvs.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_NVS_H_
+#define _SOC_NVS_H_
+
+#include <intelblocks/nvs.h>
+
+#endif
diff --git a/src/soc/intel/elkhartlake/include/soc/pmc.h b/src/soc/intel/elkhartlake/include/soc/pmc.h
new file mode 100644
index 0000000000..59bee8f4a3
--- /dev/null
+++ b/src/soc/intel/elkhartlake/include/soc/pmc.h
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_ELKHARTLAKE_PMC_H_
+#define _SOC_ELKHARTLAKE_PMC_H_
+
+/* PCI Configuration Space (D31:F2): PMC */
+#define PWRMBASE 0x10
+#define ABASE 0x20
+
+/* Memory mapped IO registers in PMC */
+#define GEN_PMCON_A 0x1020
+#define DC_PP_DIS (1 << 30)
+#define DSX_PP_DIS (1 << 29)
+#define AG3_PP_EN (1 << 28)
+#define SX_PP_EN (1 << 27)
+#define ALLOW_ICLK_PLL_SD_INC0 (1 << 26)
+#define GBL_RST_STS (1 << 24)
+#define DISB (1 << 23)
+#define ALLOW_OPI_PLL_SD_INC0 (1 << 22)
+#define MEM_SR (1 << 21)
+#define ALLOW_SPXB_CG_INC0 (1 << 20)
+#define ALLOW_L1LOW_C0 (1 << 19)
+#define MS4V (1 << 18)
+#define ALLOW_L1LOW_OPI_ON (1 << 17)
+#define SUS_PWR_FLR (1 << 16)
+#define PME_B0_S5_DIS (1 << 15)
+#define PWR_FLR (1 << 14)
+#define ALLOW_L1LOW_BCLKREQ_ON (1 << 13)
+#define DIS_SLP_X_STRCH_SUS_UP (1 << 12)
+#define SLP_S3_MIN_ASST_WDTH_MASK (3 << 10)
+#define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10)
+#define SLP_S3_MIN_ASST_WDTH_1MS (1 << 10)
+#define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10)
+#define SLP_S3_MIN_ASST_WDTH_2S (3 << 10)
+#define HOST_RST_STS (1 << 9)
+#define ESPI_SMI_LOCK (1 << 8)
+#define S4MAW_MASK (3 << 4)
+#define S4MAW_1S (1 << 4)
+#define S4MAW_2S (2 << 4)
+#define S4MAW_3S (3 << 4)
+#define S4MAW_4S (0 << 4)
+#define S4ASE (1 << 3)
+#define PER_SMI_SEL_MASK (3 << 1)
+#define SMI_RATE_64S (0 << 1)
+#define SMI_RATE_32S (1 << 1)
+#define SMI_RATE_16S (2 << 1)
+#define SMI_RATE_8S (3 << 1)
+#define SLEEP_AFTER_POWER_FAIL (1 << 0)
+
+#define GEN_PMCON_B 0x1024
+#define SLP_STR_POL_LOCK (1 << 18)
+#define ACPI_BASE_LOCK (1 << 17)
+#define PM_DATA_BAR_DIS (1 << 16)
+#define WOL_EN_OVRD (1 << 13)
+#define BIOS_PCI_EXP_EN (1 << 10)
+#define PWRBTN_LVL (1 << 9)
+#define SMI_LOCK (1 << 4)
+#define RTC_BATTERY_DEAD (1 << 2)
+
+#define ETR 0x1048
+#define CF9_LOCK (1 << 31)
+#define CF9_GLB_RST (1 << 20)
+
+#define SSML 0x104C
+#define SSML_SSL_DS (0 << 0)
+#define SSML_SSL_EN (1 << 0)
+
+#define SSMC 0x1050
+#define SSMC_SSMS (1 << 0)
+
+#define SSMD 0x1054
+#define SSMD_SSD_MASK (0xffff << 0)
+
+#define PRSTS 0x1810
+
+#define S3_PWRGATE_POL 0x1828
+#define S3DC_GATE_SUS (1 << 1)
+#define S3AC_GATE_SUS (1 << 0)
+
+#define S4_PWRGATE_POL 0x182c
+#define S4DC_GATE_SUS (1 << 1)
+#define S4AC_GATE_SUS (1 << 0)
+
+#define S5_PWRGATE_POL 0x1830
+#define S5DC_GATE_SUS (1 << 15)
+#define S5AC_GATE_SUS (1 << 14)
+
+#define DSX_CFG 0x1834
+#define REQ_CNV_NOWAKE_DSX (1 << 4)
+#define REQ_BATLOW_DSX (1 << 3)
+#define DSX_EN_WAKE_PIN (1 << 2)
+#define DSX_DIS_AC_PRESENT_PD (1 << 1)
+#define DSX_EN_LAN_WAKE_PIN (1 << 0)
+#define DSX_CFG_MASK (0x1f << 0)
+
+#define PMSYNC_TPR_CFG 0x18C4
+#define PCH2CPU_TPR_CFG_LOCK (1 << 31)
+#define PCH2CPU_TT_EN (1 << 26)
+
+#define PCH_PWRM_ACPI_TMR_CTL 0x18FC
+#define GPIO_GPE_CFG 0x1920
+#define GPE0_DWX_MASK 0xf
+#define GPE0_DW_SHIFT(x) (4*(x))
+
+#define PMC_GPP_G 0x0
+#define PMC_GPP_B 0x1
+#define PMC_GPP_A 0x2
+#define PMC_GPP_R 0x3
+#define PMC_GPP_S 0x4
+#define PMC_GPD 0x5
+#define PMC_GPP_H 0x6
+#define PMC_GPP_D 0x7
+#define PMC_GPP_F 0x8
+#define PMC_GPP_C 0xA
+#define PMC_GPP_E 0xB
+
+#define GBLRST_CAUSE0 0x1924
+#define GBLRST_CAUSE0_THERMTRIP (1 << 5)
+#define GBLRST_CAUSE1 0x1928
+
+#define CPPMVRIC 0x1B1C
+#define XTALSDQDIS (1 << 22)
+
+#define IRQ_REG ACTL
+#define SCI_IRQ_ADJUST 0
+#define ACTL 0x1BD8
+#define PWRM_EN (1 << 8)
+#define ACPI_EN (1 << 7)
+#define SCI_IRQ_SEL (7 << 0)
+
+#define SCIS_IRQ9 0
+#define SCIS_IRQ10 1
+#define SCIS_IRQ11 2
+#define SCIS_IRQ20 4
+#define SCIS_IRQ21 5
+#define SCIS_IRQ22 6
+#define SCIS_IRQ23 7
+#endif
diff --git a/src/soc/intel/elkhartlake/include/soc/ramstage.h b/src/soc/intel/elkhartlake/include/soc/ramstage.h
new file mode 100644
index 0000000000..8188fbdb84
--- /dev/null
+++ b/src/soc/intel/elkhartlake/include/soc/ramstage.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_RAMSTAGE_H_
+#define _SOC_RAMSTAGE_H_
+
+#include <device/device.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <soc/soc_chip.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params);
+void soc_init_pre_device(void *chip_info);
+
+#endif
diff --git a/src/soc/intel/elkhartlake/include/soc/serialio.h b/src/soc/intel/elkhartlake/include/soc/serialio.h
new file mode 100644
index 0000000000..e42af5f781
--- /dev/null
+++ b/src/soc/intel/elkhartlake/include/soc/serialio.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SERIALIO_H_
+#define _SERIALIO_H_
+
+enum {
+ PchSerialIoDisabled,
+ PchSerialIoPci,
+ PchSerialIoHidden,
+ PchSerialIoLegacyUart,
+ PchSerialIoSkipInit
+};
+
+enum {
+ PchSerialIoIndexI2C0,
+ PchSerialIoIndexI2C1,
+ PchSerialIoIndexI2C2,
+ PchSerialIoIndexI2C3,
+ PchSerialIoIndexI2C4,
+ PchSerialIoIndexI2C5,
+};
+
+enum {
+ PchSerialIoIndexGSPI0,
+ PchSerialIoIndexGSPI1,
+ PchSerialIoIndexGSPI2,
+ PchSerialIoIndexGSPI3,
+};
+
+enum {
+ PchSerialIoIndexUART0,
+ PchSerialIoIndexUART1,
+ PchSerialIoIndexUART2,
+};
+
+#endif
diff --git a/src/soc/intel/elkhartlake/include/soc/usb.h b/src/soc/intel/elkhartlake/include/soc/usb.h
new file mode 100644
index 0000000000..247b0ba554
--- /dev/null
+++ b/src/soc/intel/elkhartlake/include/soc/usb.h
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#ifndef _SOC_USB_H_
+#define _SOC_USB_H_
+
+#include <stdint.h>
+
+/* Per Port HS Transmitter Emphasis */
+#define USB2_EMP_OFF 0
+#define USB2_DE_EMP_ON 1
+#define USB2_PRE_EMP_ON 2
+#define USB2_DE_EMP_ON_PRE_EMP_ON 3
+
+/* Per Port Half Bit Pre-emphasis */
+#define USB2_FULL_BIT_PRE_EMP 0
+#define USB2_HALF_BIT_PRE_EMP 1
+
+/* Per Port HS Preemphasis Bias */
+#define USB2_BIAS_0MV 0
+#define USB2_BIAS_11P25MV 1
+#define USB2_BIAS_16P9MV 2
+#define USB2_BIAS_28P15MV 3
+#define USB2_BIAS_39P35MV 5
+#define USB2_BIAS_45MV 6
+#define USB2_BIAS_56P3MV 7
+
+struct usb2_port_config {
+ uint8_t enable;
+ uint8_t ocpin;
+ uint8_t tx_bias;
+ uint8_t tx_emp_enable;
+ uint8_t pre_emp_bias;
+ uint8_t pre_emp_bit;
+};
+
+/* USB Overcurrent pins definition */
+enum {
+ OC0 = 0,
+ OC1,
+ OC2,
+ OC3,
+ OC4,
+ OC5,
+ OC6,
+ OC7,
+ OCMAX,
+ OC_SKIP = 0xff, /* Skip OC programming */
+};
+
+/* Standard USB Port based on length:
+ * - External
+ * - Back Panel
+ * - OTG
+ * - M.2
+ * - Internal device down */
+
+#define USB2_PORT_EMPTY { \
+ .enable = 0, \
+ .ocpin = OC_SKIP, \
+ .tx_bias = USB2_BIAS_0MV, \
+ .tx_emp_enable = USB2_EMP_OFF, \
+ .pre_emp_bias = USB2_BIAS_0MV, \
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* Length = 11.5"-12" */
+#define USB2_PORT_LONG(pin) { \
+ .enable = 1, \
+ .ocpin = (pin), \
+ .tx_bias = USB2_BIAS_39P35MV, \
+ .tx_emp_enable = USB2_PRE_EMP_ON, \
+ .pre_emp_bias = USB2_BIAS_56P3MV, \
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* Length = 6"-11.49" */
+#define USB2_PORT_MID(pin) { \
+ .enable = 1, \
+ .ocpin = (pin), \
+ .tx_bias = USB2_BIAS_0MV, \
+ .tx_emp_enable = USB2_PRE_EMP_ON, \
+ .pre_emp_bias = USB2_BIAS_56P3MV, \
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* Length = 3"-5.99" */
+#define USB2_PORT_SHORT(pin) { \
+ .enable = 1, \
+ .ocpin = (pin), \
+ .tx_bias = USB2_BIAS_39P35MV, \
+ .tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \
+ .pre_emp_bias = USB2_BIAS_39P35MV, \
+ .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \
+}
+
+/* Max TX and Pre-emp settings */
+#define USB2_PORT_MAX(pin) { \
+ .enable = 1, \
+ .ocpin = (pin), \
+ .tx_bias = USB2_BIAS_56P3MV, \
+ .tx_emp_enable = USB2_PRE_EMP_ON, \
+ .pre_emp_bias = USB2_BIAS_56P3MV, \
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* Type-C Port, no BC1.2 charge detect module / MUX
+ * Length = 3.0" - 9.00" */
+#define USB2_PORT_TYPE_C(pin) { \
+ .enable = 1, \
+ .ocpin = (pin), \
+ .tx_bias = USB2_BIAS_0MV, \
+ .tx_emp_enable = USB2_PRE_EMP_ON, \
+ .pre_emp_bias = USB2_BIAS_56P3MV, \
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
+}
+
+struct usb3_port_config {
+ uint8_t enable;
+ uint8_t ocpin;
+ uint8_t tx_de_emp;
+ uint8_t tx_downscale_amp;
+};
+
+#define USB3_PORT_EMPTY { \
+ .enable = 0, \
+ .ocpin = OC_SKIP, \
+ .tx_de_emp = 0x00, \
+ .tx_downscale_amp = 0x00, \
+}
+
+#define USB3_PORT_DEFAULT(pin) { \
+ .enable = 1, \
+ .ocpin = (pin), \
+ .tx_de_emp = 0x0, \
+ .tx_downscale_amp = 0x00, \
+}
+
+#endif
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-18 20:09:56 +0000