diff options
Diffstat (limited to 'src/soc/intel/denverton_ns')
| -rw-r--r-- | src/soc/intel/denverton_ns/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/bootblock/bootblock.c | 17 |
2 files changed, 13 insertions, 12 deletions
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 0ce0d5bdd1..713aae60df 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -108,14 +108,6 @@ config DCACHE_BSP_STACK_SIZE hex default 0x10000 -config CPU_MICROCODE_CBFS_LOC - hex - default 0xfff20040 - -config CPU_MICROCODE_CBFS_LEN - hex - default 0x0ff80 - config CPU_BCLK_MHZ int default 100 diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index f75de1f2d0..47c76b5acd 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -31,10 +31,19 @@ const FSPT_UPD temp_ram_init_params = { .Reserved = {0}, }, .FsptCoreUpd = { - .MicrocodeRegionBase = - (UINT32)CONFIG_CPU_MICROCODE_CBFS_LOC, - .MicrocodeRegionLength = - (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN, + /* + * It is a requirement for firmware to have Firmware Interface Table + * (FIT), which contains pointers to each microcode update. + * The microcode update is loaded for all logical processors before + * cpu reset vector. + * + * All SoC since Gen-4 has above mechanism in place to load microcode + * even before hitting CPU reset vector. Hence skipping FSP-T loading + * microcode after CPU reset by passing '0' value to + * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength. + */ + .MicrocodeRegionBase = 0, + .MicrocodeRegionLength = 0, .CodeRegionBase = (UINT32)(0x100000000ULL - CONFIG_ROM_SIZE), .CodeRegionLength = (UINT32)CONFIG_ROM_SIZE, |