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-rw-r--r--src/soc/intel/common/block/cpu/cpulib.c21
-rw-r--r--src/soc/intel/common/block/include/intelblocks/cpulib.h3
2 files changed, 24 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index dac654fea6..0ac8dda1a4 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -8,6 +8,7 @@
#include <intelblocks/cpulib.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/msr.h>
+#include <soc/soc_chip.h>
#include <stdint.h>
/*
@@ -254,6 +255,26 @@ uint32_t cpu_get_max_ratio(void)
return ratio_max;
}
+void configure_tcc_thermal_target(void)
+{
+ const config_t *conf = config_of_soc();
+ msr_t msr;
+
+ /* Set TCC activation offset */
+ msr = rdmsr(MSR_PLATFORM_INFO);
+ if ((msr.lo & BIT(30)) && conf->tcc_offset) {
+ msr = rdmsr(MSR_TEMPERATURE_TARGET);
+ msr.lo &= ~(0xf << 24);
+ msr.lo |= (conf->tcc_offset & 0xf) << 24;
+ wrmsr(MSR_TEMPERATURE_TARGET, msr);
+ }
+ msr = rdmsr(MSR_TEMPERATURE_TARGET);
+ /* Time Window Tau Bits [6:0] */
+ msr.lo &= ~0x7f;
+ msr.lo |= 0xe6; /* setting 100ms thermal time window */
+ wrmsr(MSR_TEMPERATURE_TARGET, msr);
+}
+
uint32_t cpu_get_bus_clock(void)
{
/* CPU bus clock is set by default here to 100MHz.
diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h
index 73f4e38332..09f5e45577 100644
--- a/src/soc/intel/common/block/include/intelblocks/cpulib.h
+++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h
@@ -133,6 +133,9 @@ uint32_t cpu_get_min_ratio(void);
*/
uint32_t cpu_get_max_ratio(void);
+/* Thermal throttle activation offset */
+void configure_tcc_thermal_target(void);
+
/*
* cpu_get_power_max calculates CPU TDP in mW
*/