diff options
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/cse/Kconfig | 25 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cse/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cse/disable_heci.c | 36 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cse.h | 12 |
4 files changed, 69 insertions, 7 deletions
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 23e08e636a..1a112bd68a 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -14,13 +14,32 @@ config DISABLE_HECI1_AT_PRE_BOOT Mainboard users to select this config to make HECI1 `function disable` prior to handing off to payload. -config SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM +config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_SBI bool default y if HECI_DISABLE_USING_SMM select SOC_INTEL_COMMON_BLOCK_P2SB help - Use this config to include common CSE block to make HECI function - disable in SMM mode + Use this config to allow common CSE block to make HECI1 function disable + in the SMM mode. From CNL PCH onwards,`HECI1` disabling can only be done + using the non-posted sideband write after FSP-S sets the postboot_sai + attribute. + +config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC + bool + default n + select SOC_INTEL_COMMON_BLOCK_PMC + help + Use this config to allow common CSE block to make HECI1 function disable + using PMC IPC command `0xA9`. From TGL PCH onwards, disabling heci1 + device using PMC IPC doesn't required to run the operation in SMM. + +config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR + bool + default n + select SOC_INTEL_COMMON_BLOCK_PCR + help + Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented) + to make `HECI1` device disable using private configuration register (PCR) write. config SOC_INTEL_CSE_LITE_SKU bool diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 0e5dcdabf2..11a489178e 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -2,7 +2,8 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c -smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += disable_heci.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += disable_heci.c ramstage-$(CONFIG_SOC_INTEL_CSE_SET_EOP) += cse_eop.c diff --git a/src/soc/intel/common/block/cse/disable_heci.c b/src/soc/intel/common/block/cse/disable_heci.c index 1256fd1810..ab8b3ad934 100644 --- a/src/soc/intel/common/block/cse/disable_heci.c +++ b/src/soc/intel/common/block/cse/disable_heci.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#define __SIMPLE_DEVICE__ + #include <commonlib/helpers.h> #include <console/console.h> #include <device/pci.h> @@ -15,8 +17,20 @@ #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 +/* Disable HECI using PCR */ +static void heci1_disable_using_pcr(void) +{ + soc_disable_heci1_using_pcr(); +} + +/* Disable HECI using PMC IPC communication */ +static void heci1_disable_using_pmc(void) +{ + cse_disable_mei_devices(); +} + /* Disable HECI using Sideband interface communication */ -void heci_disable(void) +static void heci1_disable_using_sbi(void) { struct pcr_sbi_msg msg = { .pid = PID_CSME0, @@ -46,3 +60,23 @@ void heci_disable(void) /* hide p2sb device */ p2sb_hide(); } + +void heci1_disable(void) +{ + if (!CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + return; + + if (ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_SBI)) { + printk(BIOS_INFO, "Disabling Heci using SBI in SMM mode\n"); + return heci1_disable_using_sbi(); + } else if (!ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC)) { + printk(BIOS_INFO, "Disabling Heci using PMC IPC\n"); + return heci1_disable_using_pmc(); + } else if (!ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR)) { + printk(BIOS_INFO, "Disabling Heci using PCR\n"); + return heci1_disable_using_pcr(); + } else { + printk(BIOS_ERR, "%s Error: Unable to make HECI1 function disable!\n", + __func__); + } +} diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 9bf35dadf6..15b7313b19 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -311,8 +311,8 @@ int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t * Returns 0 on failure and 1 on success. */ int heci_reset(void); -/* Disable HECI using Sideband interface communication */ -void heci_disable(void); +/* Disable HECI1 using Sideband interface communication */ +void heci1_disable(void); /* Reads config value from a specified offset in the CSE PCI Config space. */ uint32_t me_read_config32(int offset); @@ -489,4 +489,12 @@ bool cse_get_boot_performance_data(struct cse_boot_perf_rsp *boot_perf); /* Function to make cse disable using PMC IPC */ bool cse_disable_mei_devices(void); +/* + * SoC override API to make heci1 disable using PCR. + * + * Allow SoC to implement heci1 disable override due to PSF registers being + * different across SoC generation. + */ +void soc_disable_heci1_using_pcr(void); + #endif // SOC_INTEL_COMMON_CSE_H |