diff options
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/cpu/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cpu/car/cache_as_ram.S | 25 |
2 files changed, 33 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 16844d94b6..f02af1f6b5 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -63,6 +63,14 @@ config CAR_HAS_SF_MASKS IA32_L3_SF_MASK_x programming is required along with the data ways. This is applicable for TGL and beyond. +config SF_MASK_2WAYS_PER_BIT + bool + depends on INTEL_CAR_NEM_ENHANCED + help + In the case of non-inclusive cache architecture when two ways in + the SF mask are controlled by one bit of the SF QoS register. + This is applicable for TGL alone. + config COS_MAPPED_TO_MSB bool depends on INTEL_CAR_NEM_ENHANCED diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 5f39507373..e82406ef00 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -499,6 +499,7 @@ find_llc_subleaf: * of RW data. */ movl $0x01, %eax + mov %eax, %edx /* back up data_ways in edx */ cmp $CONFIG_DCACHE_RAM_SIZE, %ecx jnc set_eviction_mask @@ -508,6 +509,7 @@ find_llc_subleaf: */ mov $CONFIG_DCACHE_RAM_SIZE, %eax div %ecx + mov %eax, %edx /* back up data_ways in edx */ mov %eax, %ecx movl $0x01, %eax shl %cl, %eax @@ -517,6 +519,29 @@ set_eviction_mask: mov %ebx, %edi /* back up number of ways */ mov %eax, %esi /* back up the non-eviction mask */ #if CONFIG(CAR_HAS_SF_MASKS) + mov %edx, %eax /* restore data_ways in eax */ + /* + * Calculate SF masks 2: + * 1. if CONFIG_SF_MASK_2WAYS_PER_BIT: data_ways = data_ways / 2 + * 2. Program MSR 0x1892 Non-Eviction Mask #2 + * IA32_CR_SF_QOS_MASK_2 = ((1 << data_ways) - 1) + */ +#if CONFIG(SF_MASK_2WAYS_PER_BIT) + cmp $0x01, %eax /* Skip Step 1 if data_ways = 1 */ + jz program_sf2 + movl $0x01, %ecx /* Step 1 */ + shr %cl, %eax +#endif + /* Step 2 */ + mov %eax, %ecx + movl $0x01, %eax + shl %cl, %eax + subl $0x01, %eax +program_sf2: + xorl %edx, %edx + mov $IA32_CR_SF_QOS_MASK_2, %ecx + wrmsr + /* * SF mask is programmed with the double number of bits than * the number of ways |