diff options
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/cpu/car/cache_as_ram.S | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/fast_spi/fast_spi_def.h | 32 | ||||
| -rw-r--r-- | src/soc/intel/common/block/scs/sd.c | 2 |
3 files changed, 19 insertions, 19 deletions
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 02aeefe9ab..684f82786a 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -94,7 +94,7 @@ clear_var_mtrr: * MTRR_PHYS_MASK_HIGH = 0000000FFh For 40 bit addressing */ - movl $0x80000008, %eax /* Address sizes leaf */ + movl $0x80000008, %eax /* Address sizes leaf */ cpuid sub $32, %al movzx %al, %eax @@ -193,7 +193,7 @@ car_init_done: movd %mm2, %eax pushl %eax /* tsc[63:32] */ movd %mm1, %eax - pushl %eax /* tsc[31:0] */ + pushl %eax /* tsc[31:0] */ before_carstage: post_code(0x2A) diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index a389e34154..2ae56dfa7b 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -22,7 +22,7 @@ #define SPIBAR_BIOS_CONTROL 0xdc /* Bit definitions for BIOS_CONTROL */ -#define SPIBAR_BIOS_CONTROL_WPD (1 << 0) +#define SPIBAR_BIOS_CONTROL_WPD (1 << 0) #define SPIBAR_BIOS_CONTROL_LOCK_ENABLE (1 << 1) #define SPIBAR_BIOS_CONTROL_CACHE_DISABLE (1 << 2) #define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3) @@ -113,21 +113,21 @@ #define SPIBAR_FPR_MAX 5 /* Programmable values for OPMENU_LOWER(0xA8) & OPMENU_UPPER(0xAC) register */ -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ +#define SPI_OPTYPE_0 0x01 /* Write, no address */ +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 0x03 /* Write, address required */ +#define SPI_OPMENU_2 0x03 /* READ: Read Data */ +#define SPI_OPTYPE_2 0x02 /* Read, address required */ +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ +#define SPI_OPTYPE_3 0x00 /* Read, no address */ +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ +#define SPI_OPTYPE_4 0x03 /* Write, address required */ +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ +#define SPI_OPTYPE_5 0x00 /* Read, no address */ +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ +#define SPI_OPTYPE_6 0x03 /* Write, address required */ +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ #define SPI_OPTYPE_7 0x02 /* Read, address required */ #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index 66eaddf5eb..811d27354e 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -57,7 +57,7 @@ static void sd_fill_ssdt(struct device *dev) static struct device_operations dev_ops = { .read_resources = &pci_dev_read_resources, .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, + .enable_resources = &pci_dev_enable_resources, #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = &sd_fill_ssdt, #endif |