diff options
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/common/block/acpi/acpi.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/reset.c | 29 | ||||
| -rw-r--r-- | src/soc/intel/common/reset.h | 28 |
4 files changed, 45 insertions, 15 deletions
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index ea6f10e1f6..42043d740d 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -25,6 +25,7 @@ config DISPLAY_SMM_MEMORY_MAP config SOC_INTEL_COMMON_RESET bool default n + select HAVE_CF9_RESET config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE bool diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index c2f0594283..870e371233 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -18,7 +18,7 @@ #include <arch/smp/mpspec.h> #include <bootstate.h> #include <cbmem.h> -#include <cpu/intel/reset.h> +#include <cf9_reset.h> #include <cpu/intel/turbo.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c index bdd7d9198e..71a7b0f02b 100644 --- a/src/soc/intel/common/reset.c +++ b/src/soc/intel/common/reset.c @@ -1,9 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright 2017 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,21 +13,24 @@ * GNU General Public License for more details. */ -#include <arch/hlt.h> -#include <arch/io.h> -#include <cpu/intel/reset.h> +#include <arch/cache.h> +#include <cf9_reset.h> +#include <console/console.h> +#include <halt.h> #include <reset.h> -#if IS_ENABLED(CONFIG_HAVE_HARD_RESET) -void do_hard_reset(void) +#include "reset.h" + +void global_reset(void) { - /* S0->S5->S0 trip. */ - outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT); + printk(BIOS_INFO, "%s() called!\n", __func__); + cf9_reset_prepare(); + dcache_clean_all(); + do_global_reset(); + halt(); } -#endif -void do_soft_reset(void) +void do_board_reset(void) { - /* PMC_PLTRST# asserted. */ - outb(RST_CPU | SYS_RST, RST_CNT); + full_reset(); } diff --git a/src/soc/intel/common/reset.h b/src/soc/intel/common/reset.h new file mode 100644 index 0000000000..0e605d6c61 --- /dev/null +++ b/src/soc/intel/common/reset.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _INTEL_COMMON_RESET_H_ +#define _INTEL_COMMON_RESET_H_ + +/* + * Implement SoC specific global reset (i.e. a reset of both host and + * ME partitions). Usually the ME is asked to perform the reset first. + * If that doesn't work out, fall back to a manual global reset. + */ +void do_global_reset(void); + +/* Prepare for reset, run do_global_reset(), halt. */ +__noreturn void global_reset(void); + +#endif /* _INTEL_COMMON_RESET_H_ */ |