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-rw-r--r--src/soc/intel/common/block/chip/Kconfig4
-rw-r--r--src/soc/intel/common/block/chip/Makefile.inc10
-rw-r--r--src/soc/intel/common/block/chip/chip.c34
-rw-r--r--src/soc/intel/common/block/include/intelblocks/chip.h41
4 files changed, 89 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/chip/Kconfig b/src/soc/intel/common/block/chip/Kconfig
new file mode 100644
index 0000000000..273d0885e8
--- /dev/null
+++ b/src/soc/intel/common/block/chip/Kconfig
@@ -0,0 +1,4 @@
+config SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
+ bool
+ help
+ Intel Processor common soc/ chip configuration support
diff --git a/src/soc/intel/common/block/chip/Makefile.inc b/src/soc/intel/common/block/chip/Makefile.inc
new file mode 100644
index 0000000000..425d5a24c8
--- /dev/null
+++ b/src/soc/intel/common/block/chip/Makefile.inc
@@ -0,0 +1,10 @@
+ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG),y)
+
+bootblock-y += chip.c
+romstage-y += chip.c
+verstage-y += chip.c
+ramstage-y += chip.c
+smm-y += chip.c
+postcar-y += chip.c
+
+endif
diff --git a/src/soc/intel/common/block/chip/chip.c b/src/soc/intel/common/block/chip/chip.c
new file mode 100644
index 0000000000..cfec4eca39
--- /dev/null
+++ b/src/soc/intel/common/block/chip/chip.c
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <soc/pci_devs.h>
+#include <soc/soc_chip.h>
+
+const struct soc_intel_common_config *chip_get_common_soc_structure(void)
+{
+ const struct soc_intel_common_config *soc_config;
+ const config_t *config;
+ int devfn = SA_DEVFN_ROOT;
+ const struct device *dev = dev_find_slot(0, devfn);
+
+ if (!dev || !dev->chip_info)
+ die("Could not find SA_DEV_ROOT devicetree config!\n");
+
+ config = dev->chip_info;
+ soc_config = &config->common_soc_config;
+
+ return soc_config;
+}
diff --git a/src/soc/intel/common/block/include/intelblocks/chip.h b/src/soc/intel/common/block/include/intelblocks/chip.h
new file mode 100644
index 0000000000..555bdaa893
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/chip.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_CHIP_H
+#define SOC_INTEL_COMMON_BLOCK_CHIP_H
+
+#include <intelblocks/gspi.h>
+#include <drivers/i2c/designware/dw_i2c.h>
+
+enum {
+ CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */
+ CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
+};
+
+/*
+ * This structure will hold data required by common blocks.
+ * These are soc specific configurations which will be filled by soc.
+ * We'll fill this structure once during init and use the data in common block.
+ */
+struct soc_intel_common_config {
+ int chipset_lockdown;
+ struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+ struct dw_i2c_bus_config i2c[CONFIG_SOC_INTEL_I2C_DEV_MAX];
+};
+
+/* This function to retrieve soc config structure required by common code */
+const struct soc_intel_common_config *chip_get_common_soc_structure(void);
+
+#endif /* SOC_INTEL_COMMON_BLOCK_CHIP_H */