diff options
Diffstat (limited to 'src/soc/intel/common/nvm.c')
| -rw-r--r-- | src/soc/intel/common/nvm.c | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c index 791422fe30..01138da0a6 100644 --- a/src/soc/intel/common/nvm.c +++ b/src/soc/intel/common/nvm.c @@ -23,6 +23,10 @@ #include <string.h> #include <spi-generic.h> #include <spi_flash.h> +#include <soc/spi.h> +#if CONFIG_CHROMEOS +#include <vendorcode/google/chromeos/chromeos.h> +#endif #include "nvm.h" /* This module assumes the flash is memory mapped just below 4GiB in the @@ -80,3 +84,43 @@ int nvm_write(void *start, const void *data, size_t size) return -1; return flash->write(flash, to_flash_offset(start), size, data); } + +/* Read flash status register to determine if write protect is active */ +int nvm_is_write_protected(void) +{ + u8 sr1; + u8 wp_gpio = 0; + u8 wp_spi; + + if (nvm_init() < 0) + return -1; + +#if IS_ENABLED(CONFIG_CHROMEOS) + /* Read Write Protect GPIO if available */ + wp_gpio = get_write_protect_state(); +#endif + + /* Read Status Register 1 */ + if (flash->status(flash, &sr1) < 0) { + printk(BIOS_ERR, "Failed to read SPI status register 1\n"); + return -1; + } + wp_spi = !!(sr1 & 0x80); + + printk(BIOS_DEBUG, "SPI flash protection: WPSW=%d SRP0=%d\n", + wp_gpio, wp_spi); + + return wp_gpio && wp_spi; +} + +/* Apply protection to a range of flash */ +int nvm_protect(void *start, size_t size) +{ +#if IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT) + if (nvm_init() < 0) + return -1; + return spi_flash_protect(to_flash_offset(start), size); +#else + return -1; +#endif +} |