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-rw-r--r--src/soc/intel/common/block/cpu/Kconfig2
-rw-r--r--src/soc/intel/common/block/cpu/car/cache_as_ram.S2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig
index 9023b58d54..1ec7af5cd4 100644
--- a/src/soc/intel/common/block/cpu/Kconfig
+++ b/src/soc/intel/common/block/cpu/Kconfig
@@ -64,7 +64,7 @@ config USE_CAR_NEM_ENHANCED_V2
select COS_MAPPED_TO_MSB
help
This config supports INTEL_CAR_NEM_ENHANCED mode on
- TGL platform.
+ TGL platform.
config COS_MAPPED_TO_MSB
bool
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index 167342f12e..97bffb0062 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -413,7 +413,7 @@ find_llc_subleaf:
set_eviction_mask:
mov %ebx, %ecx /* back up the number of ways */
- mov %eax, %ebx /* back up the non-eviction mask*/
+ mov %eax, %ebx /* back up the non-eviction mask */
/*
* Set MSR 0xC91 IA32_L3_MASK_1 or MSR 0x1891 IA32_CR_SF_QOS_MASK_1
* This MSR contain one bit per each way of LLC