diff options
Diffstat (limited to 'src/soc/intel/common/block')
| -rw-r--r-- | src/soc/intel/common/block/cse/Kconfig | 18 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cse/cse.c | 20 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cse.h | 6 |
3 files changed, 37 insertions, 7 deletions
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 1a112bd68a..164159c702 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -1,10 +1,3 @@ -config SOC_INTEL_COMMON_BLOCK_CSE - bool - default n - help - Driver for communication with Converged Security Engine (CSE) - over Host Embedded Controller Interface (HECI) - config DISABLE_HECI1_AT_PRE_BOOT bool "Disable HECI1 at the end of boot" depends on SOC_INTEL_COMMON_BLOCK_CSE @@ -14,6 +7,17 @@ config DISABLE_HECI1_AT_PRE_BOOT Mainboard users to select this config to make HECI1 `function disable` prior to handing off to payload. +config MAX_HECI_DEVICES + int + default 6 + +config SOC_INTEL_COMMON_BLOCK_CSE + bool + default n + help + Driver for communication with Converged Security Engine (CSE) + over Host Embedded Controller Interface (HECI) + config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_SBI bool default y if HECI_DISABLE_USING_SMM diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 32f6d4f0c2..6dfe329fc4 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -988,6 +988,26 @@ bool set_cse_device_state(unsigned int devfn, enum cse_device_state requested_st return true; } +void cse_set_to_d0i3(void) +{ + if (!is_cse_devfn_visible(PCH_DEVFN_CSE)) + return; + + set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE); +} + +/* Function to set D0I3 for all HECI devices */ +void heci_set_to_d0i3(void) +{ + for (int i = 0; i < CONFIG_MAX_HECI_DEVICES; i++) { + pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(PCH_DEV_SLOT_CSE), PCI_FUNC(i)); + if (!is_cse_devfn_visible(dev)) + continue; + + set_cse_device_state(dev, DEV_IDLE); + } +} + #if ENV_RAMSTAGE /* diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 15b7313b19..c2efab15fc 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -489,6 +489,12 @@ bool cse_get_boot_performance_data(struct cse_boot_perf_rsp *boot_perf); /* Function to make cse disable using PMC IPC */ bool cse_disable_mei_devices(void); +/* Set CSE device state to D0I3 */ +void cse_set_to_d0i3(void); + +/* Function sets D0I3 for all HECI devices */ +void heci_set_to_d0i3(void); + /* * SoC override API to make heci1 disable using PCR. * |