diff options
Diffstat (limited to 'src/soc/intel/common/block')
| -rw-r--r-- | src/soc/intel/common/block/fast_spi/fast_spi_flash.c | 10 | ||||
| -rw-r--r-- | src/soc/intel/common/block/graphics/graphics.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/gspi/gspi.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/systemagent/systemagent_early.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/xhci/elog.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/xhci/xhci.c | 3 |
6 files changed, 14 insertions, 13 deletions
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index 2bc7cf1759..f896cd9a3a 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -42,7 +42,7 @@ static uint32_t fast_spi_flash_ctrlr_reg_read(struct fast_spi_flash_ctx *ctx, uint16_t reg) { uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, sizeof(uint32_t)); - return read32((void *)addr); + return read32p(addr); } /* Write to register in FAST_SPI flash controller. */ @@ -50,7 +50,7 @@ static void fast_spi_flash_ctrlr_reg_write(struct fast_spi_flash_ctx *ctx, uint16_t reg, uint32_t val) { uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, sizeof(uint32_t)); - write32((void *)addr, val); + write32p(addr, val); } /* @@ -378,7 +378,7 @@ static int fast_spi_flash_protect(const struct spi_flash *flash, /* Find first empty FPR */ for (fpr = 0; fpr < SPIBAR_FPR_MAX; fpr++) { - reg = read32((void *)fpr_base); + reg = read32p(fpr_base); if (reg == 0) break; fpr_base += sizeof(uint32_t); @@ -408,8 +408,8 @@ static int fast_spi_flash_protect(const struct spi_flash *flash, reg = SPI_FPR(start, end) | protect_mask; /* Set the FPR register and verify it is protected */ - write32((void *)fpr_base, reg); - reg = read32((void *)fpr_base); + write32p(fpr_base, reg); + reg = read32p(fpr_base); if (!(reg & protect_mask)) { printk(BIOS_ERR, "Unable to set SPI FPR %d\n", fpr); return -1; diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index dae181adf4..e9a6a5dcdc 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -148,12 +148,12 @@ static uintptr_t graphics_get_gtt_base(void) uint32_t graphics_gtt_read(unsigned long reg) { - return read32((void *)(graphics_get_gtt_base() + reg)); + return read32p(graphics_get_gtt_base() + reg); } void graphics_gtt_write(unsigned long reg, uint32_t data) { - write32((void *)(graphics_get_gtt_base() + reg), data); + write32p(graphics_get_gtt_base() + reg, data); } void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask) diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 395a14dc7b..d37b330622 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -283,14 +283,14 @@ static uint32_t gspi_read_mmio_reg(const struct gspi_ctrlr_params *p, uint32_t offset) { assert(p->mmio_base != 0); - return read32((void *)(p->mmio_base + offset)); + return read32p(p->mmio_base + offset); } static void gspi_write_mmio_reg(const struct gspi_ctrlr_params *p, uint32_t offset, uint32_t value) { assert(p->mmio_base != 0); - write32((void *)(p->mmio_base + offset), value); + write32p(p->mmio_base + offset, value); } static int gspi_ctrlr_params_init(struct gspi_ctrlr_params *p, diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 299f4c18a9..aecdfbb429 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -97,8 +97,8 @@ void sa_set_mch_bar(const struct sa_mmio_descriptor *fixed_set_resources, base = fixed_set_resources[i].base; index = fixed_set_resources[i].index; if (base >> 32) - write32((void *)(uintptr_t)(MCH_BASE_ADDRESS + index + 4), base >> 32); - write32((void *)(uintptr_t)(MCH_BASE_ADDRESS + index), + write32p((uintptr_t)(MCH_BASE_ADDRESS + index + 4), base >> 32); + write32p((uintptr_t)(MCH_BASE_ADDRESS + index), (base & 0xffffffff) | PCIEXBAR_PCIEXBAREN); } } diff --git a/src/soc/intel/common/block/xhci/elog.c b/src/soc/intel/common/block/xhci/elog.c index 8acefba40c..2f94ba6025 100644 --- a/src/soc/intel/common/block/xhci/elog.c +++ b/src/soc/intel/common/block/xhci/elog.c @@ -29,7 +29,7 @@ static bool xhci_port_wake_check(uintptr_t base, uint8_t num, uint8_t host_event for (i = 0; i < num; i++, base += 0x10) { /* Read port status and control register for the port. */ - port_status = read32((void *)base); + port_status = read32p(base); /* Ensure that the status is not all 1s. */ if (port_status == 0xffffffff) diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index a12f875bfe..9931fb641e 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -3,6 +3,7 @@ #include <acpi/acpi_device.h> #include <console/console.h> #include <device/device.h> +#include <device/mmio.h> #include <device/pci.h> #include <device/pci_ids.h> #include <drivers/usb/acpi/chip.h> @@ -68,7 +69,7 @@ static bool is_usb_port_connected(const struct xhci_usb_info *info, else port_sts_reg = (uintptr_t)res->base + info->usb3_port_status_reg + port_id * 0x10; - port_status = read32((void *)port_sts_reg); + port_status = read32p(port_sts_reg); /* Ensure that the status is not all 1s */ if (port_status == 0xffffffff) |